• Title/Summary/Keyword: Multistage Interconnection Networks

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A Study on The Efficient Multicast Algorithm of Wormhole Routing Method in Multistage Networks (다단계 네트워크에서 웜홀 라우팅 방식의 효율적인 멀티캐스트 알고리즘 연구)

  • 김소은;김창수;최계현
    • Journal of Korea Multimedia Society
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    • v.2 no.2
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    • pp.184-194
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    • 1999
  • We present a new algorithm to minimize channel contention while sending multiple messages from multiple source to overlapped destination set on Multistage Interconnection Network (MIN) which supports wormhole routed turnaround routing. The multicast tree of the U-MIN(Unicast MIN) algorithm is useful in performing messages from one source to multiple destination but gives rise to a serious channel connection in performing multiple multicast because it has been designed for only single multicast. For multiple multicast communication on MIN, we address how to implement multiple multicast services efficiently. And a SPU-MIN(Source Partitioned Unicast MIN) algorithm is proposed and shown to be superior than the U-MIN algorithm for multiple multicast. The turnaround routing algorithm based on wormhole routing technique is employed as a message sending method.

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Performance Analysis of Packet Switch Interconnection Networks with Output Buffer Modules (출구 버퍼모듈을 갖는 패킷 교환식 상호 연결 망의 성능 분석)

  • Chu, Hyeon-Seung;Park, Gyeong-Rin
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.4
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    • pp.1045-1057
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    • 1999
  • Packet-switched multistage interconnection networks(MINs) have been widely used for digital switching systems and super computers. In this paper we show that multiple packets in a switching element can move to the succeeding switching element in one network cycle by fully utilizing the cycle bandwidth. Only one packet movement was usually assumed in typical MINs. we present an analytical model for the MNs with the multiple packet movement scheme, and validate it by computer simulation. Comparisons with the traditional MINs of single packet movement reveal that the throughput is increased up to about 30% for practical size MINs. Similar result was also obtained for delays. The performance increase is more significant when the network traffic is nonuniform.

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Diagnosis of Multiple Crosstalk-Faults in Optical Cross Connects for Optical Burst Switching (광 버스트 스위칭을 위한 광 교환기에서의 다중 누화고장 진단기법)

  • 김영재;조광현
    • Journal of Institute of Control, Robotics and Systems
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    • v.9 no.3
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    • pp.251-258
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    • 2003
  • Optical Switching Matrix (OSM) or Optical Multistage Interconnection Networks (OMINs) comprising photonic switches have been studied extensively as important interconnecting blocks for Optical Cross Connects (OXC) based on Optical Burst Switching (OBS). A basic element of photonic switching networks is a 2$\times$2 directional coupler with two inputs and two outputs. This paper is concerned with the diagnosis of multiple crosstalk-faults in OSM. As the network size becomes larger in these days, the conventional diagnosis methods based on tests and simulation become inefficient, or even more impractical. We propose a simple and easily implementable algorithm for detection and isolation of the multiple crosstalk-faults in OSM. Specifically. we develop an algorithm for isolation of the source fault in switching elements whenever the multiple crosstalk-faults arc detected in OSM. The proposed algorithm is illustrated by an example of 16$\times$16 OSM.

The Performance of Banyan Type ATM Switch using Monotonic Buffering Scheme (단조 버퍼링 방식을 이용한 Banyan형 ATM 스위치의 성능평가)

  • 김범식;우찬일;신인철
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 1997.11a
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    • pp.147-161
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    • 1997
  • In the future, the performance of B-lSDN offering the multimedia and a various service depends on the performance of switch that is the important factor consisting of network. Bufferless banyan network consisted of MIN(multistage interconnection network) selected for- the fabric of ATM switch and has a limitation of performance because of blocking. Input buffered banyan networks with FIFO(first-in first-out) buffering scheme for the reduction of blocking and the cell bypass queueing theory for the reduction of HOL(head of line) blocking were seperately compared of the performance of switch. Specially input buffered banyan networks were applied monotonic buffering scheme that was proposed. As a result of simulation, Buffered Banyan Network with cell bypass queueing theory showed better performance than FIFO type input buffered Banyan network. Monotonic increase buffering scheme showed better performance than Monotonic decrease buffering scheme.

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Rearrangeability of Reverse Shuffle / Exchange Networks (역 셔플익스체인지 네트워크의 재정돈성)

  • Park, Byoung-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.7
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    • pp.1842-1850
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    • 1997
  • This paper proposes a new rearrangeable algorithm in multistage reverse shuffle/exchange network. The best known lower bound of stages for rearrangeability in symmetric network is 2logN-1 stages. However, it has never been proved for nonsymmetric networks before. Currently, the best upper bound for the rearrangeability of a shuffle/exchange network in nonsymmetric network is 3logN-3 stages. We describe the rearrangeability of reverse shuffle/exchange multistage interconnection network on every arbitrary permutation with $N{\le}16$. This rearrangeability can be established by setting one more stages in the middle stage of the network to allow the reduced network to be topological equivalent to a class of rearrangeable networks. The results in this paper enable us to establish an upper bound, 2logN stages for rearrangeable reverse shuffle/exchange network with $N{\le}16$, and leads to the possibility of this bound when $N{\le}16$.

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Enhanced Cube Network for the High Reliability (고 신뢰성 큐브 네트웍)

  • Mun Youngsong
    • Journal of Internet Computing and Services
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    • v.4 no.6
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    • pp.25-31
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    • 2003
  • Multistage Interconnection networks (MIN) for the high performance computing and communications must be efficient and reliable. While a number of fault tolerance schemes have been developed, some of them are not efficient enough with respect to all evaluation measures or overheads of others are too significant. In this paper we develop a new efficient fault tolerant MIN which displays high reliability and fault tolerance capability using a simple structure. Structure and reliabilities of Enhanced Cube Network are evaluated and compared with previous designs to show the effectiveness of new design.

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A Study on the Multiple Fault-Tolerant Multipath Multistage Interconnection Network (다중 고정이 허용되는 다중경로 다단상호접속망에 관한 연구)

  • 김대호;임채택
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.972-982
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    • 1988
  • In multiprocessor systems, there are Omega network and M network among various MIN's which interconnect the processor and memory modules. Both one-path Omega network and two-path M network are composed of Log2N stages. In this paper, Augmented M network (AMN) with 2**k+1 paths and Augmented Omega network (AON) with 2**k paths are proposed. The proposed networks can be acomplished by adding K stage(s) to M network and Omega network. Using destination tag, routing algorithm for AMN and AON becomes simple and multiple faults are tolerant. By evaluating RST(request service time) performance of AMN and AON with (Log2N)+K stages, we demonstrated the fact that MMIN (AMN) with 2**k+1 paths performs better than MMIN(AON) with 2**k+1. paths.

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A Multicast ATM Switch Architecture using Shared Bus and Shared Memory Switch (공유 버스와 공유 메모리 스위치를 이용한 멀티캐스트 ATM 스위치 구조)

  • 강행익;박영근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8B
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    • pp.1401-1411
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    • 1999
  • Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

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Design and Performance Evaluation of a Fault-Tolerant Input-Buffered ATM Switch based on Multistage Interconnection Networks (다단계 상호연결 네트워크에 기반한 입력버퍼형 오류허용 ATM 스위치의 설계 및 성능 평가)

  • Sin, Won-Cheol;Son, Yu-Ik
    • The KIPS Transactions:PartC
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    • v.8C no.3
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    • pp.319-326
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    • 2001
  • 본 논문에서는 다단계상호연결 네트워크에 기반한 입력버퍼 구조의 ATM 스위치에 관해서 언급한다. 제안된 방법은 HOL 블록킹으로 인해 균일 트래픽(uniform traffic) 하에서 최대 약 58.6%의 처리율을 넘지 못하는 문제를 해결 할 수 있는 방법을 제시하며, 또한 오류허용 기능을 확장시키기 위하여 베이스라인 네트워크에서 버디 연결 매핑 및 제한연결 매핑 특성을 이용한 다중경로를 제공할 수 있는 버퍼 기법에 관하여 언급한다. 시뮬레이션에 의한 성능 평가 결과, 기존 방식과 비교하여 좋은 처리율과 셀 손실율을 보였으며, 더욱이 오류 스위치의 증가에도 불구하고 처리율의 수준은 적정한 셀 지연 범위 내에서 유지될 수 있음을 보여주고 있다.

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Modeling and Performance Evaluation of Multistage Interconnection Networks with USB Scheme (USB방식을 적용한 MIN 기반 교환기 구조의 모델링 및 성능평가)

  • 홍유지;추현승;윤희용
    • Journal of the Korea Society for Simulation
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    • v.11 no.1
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    • pp.71-82
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    • 2002
  • One of the most important things in the research for MIN-based switch operation the management scheme of network cycle. In the traditional MIN, when the receving buffer module is empty, the sell has to move forward the front-most buffer position by the characteristic of the conventional FIFO queue. However, most of buffer modules are almost always full for practical amount of input loads. The long network cycle of the traditional scheme is thus a substantial waste of bandwidth. In this paper, we propose the modeling method for the input and multi-buffered MIN with unit step buffering scheme, In spite of simplicity, simulation results show that the proposed model is very accurate comparing to previous modeling approaches in terms of throughput and the trend of delay.

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