• 제목/요약/키워드: Multiply paper

검색결과 157건 처리시간 0.024초

IEEE 754 단정도 부동 소수점 연산용 곱셈기 설계 (Design of a Floating Point Multiplier for IEEE 754 Single-Precision Operations)

  • 이주훈;정태상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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    • pp.778-780
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    • 1999
  • Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

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디지탈 뉴런프로세서의 구현에 관한 연구 (On the Implementation of the Digital Neuron Processor)

  • 홍봉화;이지영
    • 한국컴퓨터정보학회논문지
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    • 제4권2호
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    • pp.27-38
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    • 1999
  • 본 논문에서는 캐리 전파가 없어 고속 연산이 가능한 잉여수체계(Residue Number System)를 이용하여 고속의 디지털 뉴런 프로세서를 제안하였다. 제안된 뉴런프로세서는 MAC (Multiply And Accumulator) 연산부, 몫연산부, 시그모이드(Sigmoid)함수 연산부로 구성되며, 0.8$\mu$m CMOS공정으로 설계되었다 실험결과, 본 논문에서 구현한 디지털 뉴런프로세서는 19.2nsec의 속도를 보였으며, 실수연산기로 구현한 뉴런프로세서에 비하여 약1/2정도 하드웨어 크기를 줄일 수 있었다.

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적응 횡단선 필터에서 재순환 버퍼를 이용한 수렴속도 개선 (An Improvement of Convergence Speed with Recycling Buffer in Adaptive Transversal Filter)

  • 김원균;임경모;김광준;나상동;배철수
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 1998년도 추계종합학술대회
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    • pp.574-577
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    • 1998
  • In this paper, a new simple and efficient technique to improve the convergence speed of LMS algorithm is proposed in an interference-limited multi-path fading environment as encountered in indoor wireless communications. The convergence characteristics of the proposed algorithm, whose coefficients are multiply adapted in a symbol time period by recycling the received data, are analyzed to prove theoretically the improvement of convergence speed. The theoretical analysis shows that the data-recycling in technique can increase convergence speed by (B+1) times without increasing the computational complexity substantially where B is the number of recycled data. The results of the computer simulation demonstrate that the simulation results are in accordance with the theoretical analysis and the superiority of the filter algorithm.

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수퍼스칼라 마이크로프로세서용 부동 소수점 승산기의 설계 (A design of floating-point multiplier for superscalar microprocessor)

  • 최병윤;이문기
    • 한국통신학회논문지
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    • 제21권5호
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    • pp.1332-1344
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    • 1996
  • This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

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휴대단말용 RISC 프로세서의 32비트 MAC 구조 (32-bit MAC Architecture of a RISC Processor for Portable Terminals)

  • 정갑천;박성모
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.357-360
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    • 2000
  • In this paper, we designed 32-Hit MAC architecture of a RISC Processor for portable terminals such as cellular telephones, personal digital assistants, notebooks, etc. In order to have minimum area with best performance, the MAC performs 32 by 8 multiplication per cycle, with early termination circuit that enables multiply cycles depend on the value of multiplier. It uses the sign bit of a partial product and two extra bits for sign extension, The MAC is modeled and simulated in RTL using VHDL. The MAC is synthesized using IDEC C-631 Cell library based on 0.6$\mu\textrm{m}$ CMOS 1-Poly 3-metal CMOS technology.

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A DSP Architecture for High-Speed FFT in OFDM Systems

  • Lee, Jae-Sung;Lee, Jeong-Hoo;SunWoo, Myung-H.;Moh, Sang-Man;Oh, Seong-Keun
    • ETRI Journal
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    • 제24권5호
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    • pp.391-397
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    • 2002
  • This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 ${\mu}m$ standard cell library, and then verified the functions thoroughly.

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2개의 원형개구부가 있는 복합재료 적층판의 응력해석 (Stress Analysis of Composite Laminated Plates with 2 Collinear Circular Cutouts)

  • 이윤복;이영신
    • 한국복합재료학회:학술대회논문집
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    • 한국복합재료학회 1999년도 추계학술발표대회 논문집
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    • pp.223-226
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    • 1999
  • This paper presents the theoretical analysis method to determine the stress concentrations around the circular cutouts with various geometrical parameters. The purposes of this study are to investigate on the stress distribution around the circular cutouts due to interaction between two circular cutouts and to develop the design method in composite plates. The composite laminated plate with 2 equal collinear circular cutouts under inplane loads is treated as an quasi-isotropic, symmetric, finite, square, multiply connected and thin plate. The effects of cutout sizes, distances between two circular cutouts and inplane load conditions on stress distribution are studied in detail.

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Field measurements of wind characteristics over hilly terrain within surface layer

  • He, Y.C.;Chan, P.W.;Li, Q.S.
    • Wind and Structures
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    • 제19권5호
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    • pp.541-563
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    • 2014
  • This paper investigates the topographic effects on wind characteristics over hilly terrain, based on wind data recorded at a number of meteorological stations in or near complex terrain. The multiply data sources allow a more detailed investigation of the flow field than is normally possible. Vertical profiles of mean and turbulent wind components from a Sodar profiler were presented and then modeled as functions of height and wind speed. The correlations between longitudinal and vertical wind components were discussed. The phenomena of flow separation and generation of vortices were observed. The distance-dependence of the topographic effects on gust factors was revealed subsequently. Furthermore, the canyon effect was identified and discussed based on the observations of wind at a saddle point between two mountain peaks. This study aims to further understanding of the characteristics of surface wind over rugged terrain. The presented results are expected to be useful for structural design, prevention of pollutant dispersion, and validation of CFD (computational fluid dynamics) models or techniques over complex terrains.

보증분석을 위한 품질보증 기간 중 제품 교체율 추정 사례 연구 (Estimation of a Product Replacement Ratio During the Warranty Period for a Warranty Analysis)

  • 안해일
    • 산업경영시스템학회지
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    • 제35권2호
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    • pp.71-79
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    • 2012
  • In this paper, an evaluation of a product replacement ratio of irreparable items to the normally working ones is performed with a view to a warranty analysis. It is demonstrated that the replacement ratio during the warranty period can be estimated from the field data collected during the period of operation, and one can provide the management with a useful information regarding the appropriateness for the warranty period, which is vital to the product marketing strategy. Although warranty data usually take the form of multiply right censored interval data, the conventional reliability analysis method seems to be good enough as in this case. More sophisticated method such as warranty cost analysis and 2-dimensional warranty analysis is yet desired.

Eddy current 동력계의 부하와 와전류의 직진성 관련 연구 (Linearity study for the field coil current and the load of eddy current dynamometer)

  • 문병수
    • 한국공작기계학회:학술대회논문집
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    • 한국공작기계학회 2000년도 춘계학술대회논문집 - 한국공작기계학회
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    • pp.66-72
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    • 2000
  • Commercial eddy current dynamometers control the torque of ratating body (poer supply machine) with the field coil current being operated as a braking force. In this paper, we studied about the relation between the field coil current and the torque load of eddy current dynamometer. By the torque measuring analysis of eddy current dynamometer, it is linear relation between the brake force measured from the torque meter (e.g. load cell, strain gage or spring balance etc.) which is installed at the case of dynamometer and the multiply of shaft rpm by the square of field coil current (N$\times$Ia2). To prove the relation, it was experimented and showed that the torque operated by the rotating body can be measured with the shaft rpm and the field coil current of eddy current dynamometer. This result shows a possibility that eddy current dynamometer can measures the torque of rotating body without special torque measuring devices.

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