• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.54-65
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• 1992

A huge amount of multiplications is required for 2-D filtering on the image data, making it difficult to implement a real-time quincuncial interpolator. In this paper, efficient design technique and VLSI structures for 2-D multipleierless filter are presented. In the filter design, by introducing an efficient scheme for discretizing the frequency response of the prototype filter, it is shown that a significant amount of the computational burden required in the conventional techniques, such as local search, branch and bound techniques, could be saved. In the case of 5$\times$5 filter, it is found that the design technique described in this paper could save about 80% of the computation time, compared to the conventional methods, while providing a comparable performance. For a hardware implementation, two different VLSI structures for 2-D multiplierless filter are also introduced in the paper : One is for block parallel processing and the other for scan-line parallel processing. In both structure, the AP(area-period) figure improves over Wu's structure[4].

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.249-256
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• 1986

In this paper, we propose the MDM algorithm by which one can desing an FIR filter that is maximally flat and requires no multiplication. We use the modified MAXFLAT subroutive of Kaiser to achieve the maximally-flat characteristics. The filter coefficients are encoded in MDM-code and the optimal stepsize is determined the steepest- descent method. Simulation results shows that the FIR filter designed is almost maximally-flat in passband, but has about -30dB ripples in stopband due to MDM quantization error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.166-175
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• 1990

The conventional FIR filters can be very expensive to implement due to the complexity of multibit multipliers. This paper presents an new type of multiplierless structure which is particularly suited to the hardware implementation of small, low cost, low power, high speed digital filters. The filter structures consisting of a transversal filter with tap coefficiented to the combination of two elements of the set {0, $\pm$$2^n$;n = integer} and cascaded with a integrator are proposed. Performance has been tested via simulation on a digital computer, and the results show that the response characteristics of presented filters are as equally good as those of conventional finitewordlength filters.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.123-128
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• 1994

Hardware realization of a digital 2-D homomorphic filter for real time contrast enhancement of video signal is presented. In homomorphic filter, logarithmic and exponential conversion used the memory lookup table method and because the hardware is implemented by multiplierless TTL devices, it can be designed to specific IC. The contrast gain can be controlled externally and the transfer function of homomorphic filter can be easily varied by the change of lookup table memory data.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.1008-1014
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• 2002

This paper is concerned about multiplierless interpolation FIR filters. In this paper, we propose a filter that performs T tap 1:N interpolation FIR filter operation with B-bit inputs without using multipliers. This is done by applying a method which converts a 2s complement multi-bits input to multiple single-bit inputs and a lookup table minimization method which reduces the size of lookup tables by use of the symmetry of filter coefficients and the symmetry of each lookup table. Two FIR filters are implemented using the methods proposed in this paper. Each of the two filters respectively follows the two design parameters in the specification of IMT-2000. Those two FIR filters have an advantage that the number of required gates is reduced up to 70% comparing to that of a conventional transversal FIR filter.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.183-186
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• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.