• Title/Summary/Keyword: Multiple voltages

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Development of a Coordinated Voltage Regulation Scheme in Distribution Networks with Multiple Distributed Generations (협조 제어를 이용한 분산전원 연계 배전계통의 전압조정 방식 개발)

  • Oh, Yun-Sik;Cho, Kyu-Jung;Kim, Min-Sung;Kim, Ji-Soo;Kim, Chul-Hwan
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.9
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    • pp.1309-1316
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    • 2017
  • As penetration level of Distributed Generations (DGs) on weak distribution networks gets higher, voltage rise problem can often occur due to reverse power which is not expected in conventional distribution networks. It, however, cannot be effectively solved by using conventional voltage regulating devices such as On-Load Tap Changers (OLTCs), Step Voltage Regulators (SVRs) because those do not consider the presence of DGs when determining relevant setting parameter for voltage regulation. This paper presents a scheme for voltage regulation using coordinated control between OLTC and DGs which can actively participate in the regulation. The scheme decides which device should be operated first based on the characteristics of regulating devices, in order to prevent unnecessary operation of output changes of DG and excessive tap changing operation of OLTC. Computer simulations considering daily irradiation of PV and load curve are performed by using MATLAB Simulink and performance comparison between the presented scheme and conventional ones is also made. It can be concluded from simulation results that the scheme presented is very effective to regulate voltages in distribution networks with multiple DGs.

Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

  • Hayder, Abbas Syed;Park, Young-Jun;Kim, SangYun;Pu, Young-Gun;Yoo, Sang-Sun;Yang, Youngoo;Lee, Minjae;Hwang, Keum Choel;Lee, Kang-Yoon
    • Journal of Power Electronics
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    • v.17 no.3
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    • pp.821-834
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    • 2017
  • This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

Recognition resolution enhancement of ultrasonic sensors via multiple steps of transmitter voltages

  • Na, Seung-You;Park, Min-Sang
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10a
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    • pp.409-412
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    • 1996
  • Ultrasonic sensors are widely used in various applications due to advantages of low cost, simplicity in construction, mechanical robustness, and little environmental restriction in usage. But the main purposes of the noncontact sensing are rather narrowly confined within object detection and distance measurement. For the application of object recognition, ultrasonic sensors exhibit several shortcomings of poor directionality which results in low spatial resolution of objects, and specularity which gives frequent erroneous range readings. To resolve these problems in object recognition, an array of the sensor has been used. To improve the spatial resolution, more number of sensors are used in essence throughout the various devices of the sensor arrays. Under the disguise of a fixed number of the sensors, the array can be shifted mechanically in several steps. In this paper we propose a practical sensor resolution enhancement method using an electronic circuit accompanying the sensor array. The circuit changes the transmitter output voltage in several steps. Using the known sensor characteristics, a set of different return echo signals provide enhanced spatial resolution. The improvement is obtained with neither the cost of the increased number of the sensors nor extra mechanical devices.

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Characteristics of Si Nano-Crystal Memory

  • Kwangseok Han;Kim, Ilgweon;Hyungcheol Shin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.1
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    • pp.40-49
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    • 2001
  • We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}V_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

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A Single Inductor Dual Output Synchronous High Speed DC-DC Boost Converter using Type-III Compensation for Low Power Applications

  • Hayder, Abbas Syed;Park, Hyun-Gu;Kim, Hongin;Lee, Dong-Soo;Abbasizadeh, Hamed;Lee, Kang-Yoon
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.1
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    • pp.44-50
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    • 2015
  • This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

  • Ishihara, Shota;Xia, Zhengfan;Hariyama, Masanori;Kameyama, Michitaka
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.165-175
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    • 2010
  • This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

Probabilistic Evaluation of Voltage Quality on Distribution System Containing Distributed Generation and Electric Vehicle Charging Load

  • CHEN, Wei;YAN, Hongqiang;PEI, Xiping
    • Journal of Electrical Engineering and Technology
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    • v.12 no.5
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    • pp.1743-1753
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    • 2017
  • Since there are multiple random variables in the probabilistic load flow (PLF) calculation of distribution system containing distributed generation (DG) and electric vehicle charging load (EVCL), a Monte Carlo method based on composite sampling method is put forward according to the existing simple random sampling Monte Carlo simulation method (SRS-MCSM) to perform probabilistic assessment analysis of voltage quality of distribution system containing DG and EVCL. This method considers not only the randomness of wind speed and light intensity as well as the uncertainty of basic load and EVCL, but also other stochastic disturbances, such as the failure rate of the transmission line. According to the different characteristics of random factors, different sampling methods are applied. Simulation results on IEEE9 bus system and IEEE34 bus system demonstrates the validity, accuracy, rapidity and practicability of the proposed method. In contrast to the SRS-MCSM, the proposed method is of higher computational efficiency and better simulation accuracy. The variation of nodal voltages for distribution system before and after connecting DG and EVCL is compared and analyzed, especially the voltage fluctuation of the grid-connected point of DG and EVCL.

Vibration reduction for interaction response of a maglev vehicle running on guideway girders

  • Wang, Y.J.;Yau, J.D.;Shi, J.;Urushadze, S.
    • Structural Engineering and Mechanics
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    • v.76 no.2
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    • pp.163-173
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    • 2020
  • As a vehicle moves on multiple equal-span beams at constant speed, the running vehicle would be subjected to repetitive excitations from the beam vibrations under it. Once the exciting frequency caused by the vibrating beams coincides with any of the vehicle's frequencies, resonance would take place on the vehicle. A similar resonance phenomenon occurs on a beam subject to sequential moving loads with identical axle-intervals. To reduce both resonant phenomena of a vehicle moving on guideway girders, this study proposed an additional feedback controller based the condensed virtual dynamic absorber (C-VDA) scheme. This condensation scheme has the following advantages: (1) the feedback tuning gains required to adapt the control currents or voltages are directly obtained from the tuning forces of the VDA; (2) the condensed VDA scheme does not need additional DoFs of the absorber to control the vibration of the maglev-vehicle/guideway system. By decomposing the maglev vehicle-guideway coupling system into two sub-systems (the moving vehicle and the supporting girders), an incremental-iterative procedure associated with the Newmark method is presented to solve the two sets of sub-system equations. From the present studies, the proposed C-VDA scheme is a feasible approach to suppress the interaction response for a maglev vehicle in resonance moving on a series of guideway girders.

Current Control in Cascaded H-bridge STATCOM for Electric Arc Furnaces (전기로용 다단 H-브릿지 STATCOM의 전류제어)

  • Kwon, Byung-Ki;Jung, Seung-Ki;Kim, Tae-Hyeong;Kim, Yun-Hyun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.20 no.1
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    • pp.19-30
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    • 2015
  • A static synchronous compensator (STATCOM) applied to rapidly changing, highly unbalanced loads such as electric arc furnaces (EAFs), requires both positive-sequence and negative-sequence current control, which indicates fast response characteristics and can be controlled independently. Furthermore, a delta-connected STATCOM with cascaded H-bridge configuration accompanying multiple separate DC-sides, should have high performance zero-sequence current control to suppress a phase-to-phase imbalance in DC-side voltages when compensating for unbalanced load. In this paper, actual EAF data is analyzed to reflect on the design of current controllers and a pioneering zero-sequence current controller with a superb transient performance is devised, which generates an imaginary -axis component from the presumed response of forwarded reference. Via simulation and experiments, the performance of the positive, negative, and zero-sequence current control of a cascaded H-bridge STATCOM for EAF is verified.

A New Control Strategy for Input Voltage Sharing in Input Series Output Independent Modular DC-DC Converters

  • Yang, Wei;Zhang, Zhijie;Yang, Shiyan
    • Journal of Power Electronics
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    • v.17 no.3
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    • pp.632-640
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    • 2017
  • Input series output independent (ISOI) dc-dc converter systems are suitable for high voltage input and multiple output applications with low voltage rating switches. This paper proposes a novel control strategy consisting of one output voltage regulating (OVR) control loop and n-1 (n is the number of modules in the ISOI system) input voltage sharing (IVS) control loops. An ISOI system with the proposed control strategy can be applied to applications where the output loads of each module are the same. Under these conditions, IVS can be achieved and output voltages copying can be realized in an ISOI system. In this control strategy there is only one controller for each module and the design process of the control loops is simple. Since no central controller is needed in the system, modularity of the system is improved. The operation principle of the new control strategy is introduced and the control effect is simulated. Then the output power and voltage characteristics of an ISOI system under this new control strategy are analyzed. The stability of the proposed control strategy is explored base on a Hurwitz criterion, and the design guide line of the control strategy is given. A two module ISOI system prototype is fabricated and tested in the laboratory. Experimental results verify the effectiveness of the proposed control strategy.