• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.5
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• pp.718-725
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• 2015

This paper proposes a novel level-shifted PWM (LS-PWM) strategy for fault tolerant cascaded multilevel inverter. Most proposed fault-tolerant operation methods in many of studies are based on a phase-shifted PWM (PS-PWM) method. To apply these methods to multilevel inverter systems using LS-PWM, two additional steps will be implemented. During the occurrence of a single-inverter-cell fault, the carrier bands scheme is reconfigured and modulation levels of inverter cells are reassigned in this proposed fault-tolerant operation. The proposed strategy performs balanced three-phase line-to-line voltages and line currents when a switching device fault occurs in a cascaded multilevel inverter using LS-PWM. Simulation and experimental results are included in the paper to verify the proposed method.

• Journal of Power Electronics
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• v.15 no.2
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Power Electronics
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• v.19 no.1
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• pp.244-253
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• 2019

Finite control set model-predictive control (FCS-MPC) has received increasing attentions due to its outstanding dynamic performance. It is being widely used in power converters and multilevel inverters. However, FCS-MPC requires a lot of calculations, especially for multilevel-cascaded H-bridge (CHB) static synchronous compensators (STATCOMs), since it has to take account of all the feasible voltage vectors of inverters. Hence, an improved five-segment space vector pulse width modulation (SVPWM) method based on the non-orthogonal static reference frames is proposed. The proposed SVPWM method has a lower number of switching states and requires fewer computations than the conventional method. As a result, it makes FCS-MPC more efficient for multilevel cascaded H-bridge STATCOMs. The partial cost function is adopted to sequentially solve for the reference current and capacitor voltage. The proposed FCS-MPC method can reduce the calculation burden of the FCS-MPC strategy, and reduce both the switching frequency and power losses. Simulation and experimental results validate the excellent performance of the proposed method when compared with the conventional approach.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.4
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• pp.457-463
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• 2012

Cascaded H-bridge multilevel inverters shows a useful circuit configuration to increase the number of output voltage levels to obtain high quality output voltage. By applying the concept of the power of three to dc voltage sources, it can increase the number of output voltage levels effectively. To realize this concept, two approaches may be considered. One is to use independent dc voltage sources pre-scaled in the power of three, and the other is to use instantaneous dc voltage sources generated from a cascaded transformer, which has the secondary turn-ratios scaled in the power of three in sequence. A common feature in both approaches is to use the concept of the power of three for dc voltage sources, and a point of difference is whether it adopts a low frequency transformer or not, and where the transformer is located. According to the difference, application areas are limited and show different characteristics on THD of output voltages. We compare and analyze both approaches for their circuit configurations, voltage level generating method, THD characteristics of output voltage, efficiency, application areas, limitations, and other characteristics by experiments using 500 [W] prototypes when they generate a 27-level output voltage.

• Journal of Power Electronics
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• v.18 no.2
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.229-236
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• 2008

Recently, multilevel H-bridge inverters have become popular in medium to high power ac drive applications. One of significant advantages of them is low harmonic contents in their input line currents thanks to the transformer with multiple phase-shifted secondary windings. This paper attempts to provide basic guidelines for the design of the phase shifting transformer windings and theoretical analysis of input line current harmonics of H-bridge inverters. The part I provides the derivation of basic relationships between input and output current of the transformer and the relationship between the phase shifting characteristics and design aspects of the transformer.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.237-245
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• 2008

Recently, multilevel H-bridge inverters have become popular in medium to high power ac drive applications. One of significant advantages of them is low harmonic contents in their input line currents thanks to the transformer with multiple phase-shifted secondary windings. This paper attempts to provide basic guidelines for the design of the phase shifting transformer windings and theoretical analysis of input line current harmonics of H-bridge inverters. The part II is devoted to the analysis of the harmonic characteristics of the input line current, providing mathematical background for the equidistant phase-shifting angle distribution policy for harmonic elimination.

• Journal of Power Electronics
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• v.13 no.1
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• pp.59-69
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• 2013

An alternative technique to control multilevel inverters with vector approximations has been presented. The innovative control method utilizes specially designed two-dimensional hysteresis comparators to simplify the implementation and improve the resultant waveform. The multistage inverter designed with maximum number of levels is operated in such a way to approximate the reference voltage vector by exploiting the large number of multilevel inverter vectors. A three-stage inverter with the main high voltage stage made of three phase, six-switch and singly-fed inverter is considered for application to the proposed design. The proposed control concept is to maintain a higher voltage stage state as long as it can lead to a target vector. High and medium voltage stages controllers are based on surface hysteresis comparators to hold the switching state or to perform the necessary change to achieve its reference voltage with minimal switching losses. The low voltage stage controller is designed to approximate the target reference voltage to the nearest inverter vector using the nearest integer rounding and adjustment comparators. Model simulation and prototype test results show that the proposed control technique clearly outperforms the previous control methods.

• Journal of Power Electronics
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• v.5 no.2
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• pp.142-150
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• 2005

This paper presents a systematic approach to study the carrier based pulse width modulation (PWM) techniques applied to diode-clamped and cascade multilevel inverters by using multi-modulating patterns. This method is based on the description of controllable redundant parameters in the modulating signals. A unified mathematical formulation is presented for carrier based PWM methods, which obtains outputs similar to the corresponding space vector PWM. A full and separate control of the fundamental voltage, vector redundancies and phase redundancies can be obtained in the carrier based PWM. In this paper, the proposed PWM method and corresponding algorithm for generating multi-modulating signals will be formulated and demonstrated by our simulations.