• Journal of Mechanical Science and Technology
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• 제14권9호
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• pp.997-1004
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• 2000

The experiments were conducted by using water and paraffin slurry to investigate the effect of a chip spacing in the multichip module on the cooling characteristics from an in-line $4{\times}3$ array of discrete heat sources which were flush mounted on the top wall of a channel. The experimental parameters were chip spacing in a multichip module, heat flux of simulated VLSI chip, mass fraction of paraffin slurry, and channel Reynolds number. The removable heat flux at the same chip surface temperature decreased as the chip spacing decreased at the first and fourth rows. The local heat transfer coefficients for the paraffin slurry were larger than those for water, and the chip spacing on the local heat transfer coefficients for paraffin slurry influenced less than that for water. The enhancement factor for paraffin slurry showed the largest value at a mass fraction of 5% regardless of the chip spacing, and the enhancement factors increased as the chip spacing decreased. This means that the paraffin slurry is more effective than water for cooling of the highly integrated multichip module.

• 한국통신학회논문지
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• 제39C권3호
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• pp.234-238
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• 2014

Multichip packaging was achieved the best solution to significantly reduce thermal resistance at the same time, to increase luminance intensity in LEDs packaging application. For the packaging, thermal spreading resistance is an important parameter to get influence the total thermal performance of LEDs. In this study, silicon-based multichip light emitting diodes (LEDs) packaged module has been examined for thermal characteristics in several parameters. Compared to the general conventional single LED packaged chip module, multichip LED packaged module has many advantages of low cost, low density, small size, and low thermal resistance. This analyzed module is comprised of multichip LED array, which consists of 32 LED packaged chips with supplement power of 0.2 W at every single chip. To realize the extent of thermal distribution, the computer-aided design model of 6.4 W Si-based multichip LED module was designed and was performed by the simulation basis of actual fabrication flow. The impact of thermal distribution is analyzed in alternative ways both optimizing numbers of fins and the thickness of that heatsink. In addition, a thermal resistance model was designed and derived from analytical theory. The optimum simulation results satisfies the expectations of the design goal and the measurement of IR camera results. tart after striking space key 2 times.

• 전자공학회논문지A
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• 제31A권3호
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• 한국생산제조학회지
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• 제21권1호
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• pp.46-50
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• 2012

This paper amis at improving the heat radiation performance of thermoelectric module (TEM) for a commercialization of high-powered LED light with using a multichip LED module. In addition, a 10W multichip LED light was prepared for the heat performance on radiating of which LED light was made for a use of testing by the driving of the thermoelectric module. So, it was found that about 30% in the effect of temperature reduction was confirmed if compared with the radiation heat by heat sink only.

• 전자통신동향분석
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• 제11권1호통권39호
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• pp.29-47
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• 1996

본 고는 전자통신시스템 및 단말기의 소형화 및 고기능화를 위하여 대두되고 있는 다중칩 모듈(Multichip Module; MCM)중 Laminate기술을 기본으로 하며 대량생산이 가능한 Multichip Module-Laminate(MCM-L)기술에 대하여 논하고 있다. 본 내용에는 전기 및 열특성을 결정하는 기판재료, Laminate에서의 Via 및 Pad의 한계, MCM의 성능과 관련된 시험방법 등이 있으며, 마지막으로, 통신 및 타분야의 MCM 응용사례를 조사분석하고 향후 MCM의 기술발전방향을 예측해 보았다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.9-43
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• 1999

• 마이크로전자및패키징학회지
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• 제2권2호
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• pp.57-64
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• 1995

본 연구의 목적은 MCM제품들을 개발하기 전단계로 MCM의 설계 및 MCM 설계에 필요한 CAD에 관한 현황을 조사 및 연구한 것이다.결과적으로 현재 MCM에 관하여 풀어 야 할 문제들을 도출하였으며 차후 이보고서가 MCM 및 HIC분야의 설계 CAD 선택을 연 구하는 Engineer들에게 좋은 자료로 활용될 것으로 판단된다.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• 마이크로전자및패키징학회지
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• 제6권3호
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• pp.25-35
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• 1999

저온동시소성 또는 금속상 저온동시소성 기술은 세라믹 다층멀티칩 기술의 하나로 이 기술을 이용한 모듈은 일반 전기 부품, 고주파 및 자동차 전장에 적용되기 시작하였다. 고온동시소성 기술과 비교하여 저온동시소성 기판의 소성은 그 온도가 $1000^{\circ}C$ 이하에서 이루어지므로 전기전도도가 높은 금, 은, 구리 등의 금속을 이용하여 내부 전극을 형성할 수 있다. 금속상 저온 동시소성 기술은 소성 후의 치수안정성 (x-, y- 방향으로 수축률 0.1 % 이하)의 장점으로 모듈 내부에 수동소자를 내장할 수 있으며, 이러한 장점은 전기적 특성의 향상과 신뢰성 증가를 가져온다. 모듈의 열팽창계수 및 유전율은 조성이나 소성조건을 바꾸어 조정이 가능하다. 본 기술해설에서는 저온동시소성 또는 금속상 저온동시소성 기술에 관한 소개와 장점에 대하여 설명하였다.

• 한국산업융합학회 논문집
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• 제3권1호
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• pp.69-75
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• 2000

Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.