• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.23-26
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• 2002

In this paper, we modelize several scheduling algorithms for real-time packet filtering tasks based on the multi-threaded multi-processor architecture for the network security system like the firewall and compare the performance of the algorithms by implementing the algorithms and doing a number of empirical tasks. As the matrices of the performance we use the idle factor and the packet transfer rate. We get the idle factors and the packet transfer rates according to the transfers of the packet sizes from 64 bytes to 1500 bytes.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.488-496
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• 2000

this paper describes the design and implementation of node scheduling for MX Server that is CC-NUMA System COMSIX, the operating system of MX Server, is designed to suit for CC-NUMA Architecture. MX Server consists of up to 8 nodes, and each node is connected by SCI ring. This node scheduling scheme considers data locality for performance improvement of Oracle8i DBMS on the CC-NUMA architecture. For DBMS such as Oracle8i, a multi-threaded process may be run to tie on particular disk. We have developed a CG binding function that the multi-threaded process bound the node. Currently, We don't have an available CC-NUMA Platform. Instead of MX Server, we developed the Node scheduling scheme for multi-threaded process to suit server platform on the PC test-bed and tested completely.

• Journal of information and communication convergence engineering
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• v.18 no.2
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• pp.82-87
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• 2020

This paper discusses how to design a game server that is scalable, adaptable, and re-buildable with components. Furthermore, it explains how various implementation issues were resolved. To support adaptability, the server comprises three layers: network, user, and database. To ensure independence between the layers, each layer was designed to communicate with each other only via message queues. In this architecture, each layer can have an arbitrary number of threads; thus, scalability is guaranteed for each layer. The network layer uses input/output completion ports(IOCP), which shows the best performance on the Windows platform, it can handle up to 5,000 simultaneous connections on a typical entry-level computer, despite being built with a single-threaded user layer. To completely separate the database from the game server, the SQL code was not directly embedded in the database layer.

• The KIPS Transactions:PartC
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• v.9C no.2
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• pp.213-220
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• 2002

Distributed competing system gives a new system architecture to be taken into consideration for solving the problems of interoperability of heterogeneous systems. In the present paper, CORBA based on multi-threaded interoperates with software blocks at physically isolated hardware. We show how archives optimal CORBA system from analysis of required functions, implementations of protocols and benchmarking of system performance in the Open Multi-service Network System Environment. The core features of our CORBA system are restricted Quality of Service based on priority, timeout service and exception status information notify to the related software blocks. And the objectives are design and implementation of high performance multi-threaded middleware and satisfied with extendibility, flexibility and stability of CORBA platform.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.6
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• pp.499-506
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• 2004

The copper foil surface inspection system is necessary for the factory automation and product quality. The developed system is composed of the high speed line scan camera, the image capture board and the processing computer. For the system resource utilization and real-time processing, multi-threaded architecture is introduced. There are one image capture thread, 2 or more defect detection threads, and one defect communication thread. To process the high-speed input image data, the I/O overlap is used through the double buffering. The defect is first detected by the predetermined threshold. To cope with the light irregularity, the compensation process is applied. After defect detection, defect type is classified with the defect width, eigenvalue ratio of the defect covariance matrix and gray level of defect. In experiment, for high-speed input image data, real-time processing is possible with multi -threaded architecture, and the 89.4% of the total 141 defects correctly classified.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.215-217
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• 1999

CORBA 2.0 규격에 따라 구현돈 인터넷 Java ORB인 iORB는 Common Object Request Broker Architecture (CORBA) 객체 호출을 위한 Basic Object Adapter (BOA)를 클라이언트와 서버 객체 사이의 연결 설정과 요청 처리를 분리한 다중 쓰레드 방식으로 제공하고 있다. 본 논문은 다중 쓰레드 방식을 지원하는 iORB의 BOA 설계 및 구현에 관한 것이다.

• Information and Communications Magazine
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• v.19 no.11
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• pp.70-84
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• 2002

In this paper we discuss a multi-threaded baseband Processor capable of executing all physical layer processing of high data rate communications systems completely in software. We discuss the enabling technology for a software defined radio approach and present results for GPRS. 802.11b, and 2Mbps WCDMA. All of these protocols can be executed in real-time on the SB9600 chip using the Sandblaster core.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.13-21
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• 2013

Recently, although the number of cores on a chip multi-processor increases, multi-programming or multi-threaded programming techniques to utilize the whole cores are still insufficient. Therefore, there inevitably exist some idle cores which are not working. This results in a waste of the caches, so-called idle caches which are dedicated to those idle cores. In this research, we propose amethodology to exploit idle caches effectively as victimcaches of on-chip memory resource. In simulation results, we have achieved 19.4%and 10.2%IPC improvement in 4-core and 16-core respectively, compared to previous technique.

• The KIPS Transactions:PartA
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• v.19A no.2
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• pp.93-100
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• 2012

LLRP (Low-Level Reader Protocol) specifies an interface between RFID readers and RFID applications, also called LLRP servers and clients respectively. An LLRP server should concurrently execute various functions. This paper designs an LLRP server of a multi-threaded architecture. For that, (i) the operational procedure between LLRP servers and clients is investigated, (ii) the functional requirements of LLRP servers are presented, (iii) the operation of an LLRP server is decomposed into several threads to satisfy those functional requirements, and (iv) the operational procedure is further examined in thread-level. To validate the designed architecture, it is modeled and simulated by using the DEVS formalism which specifies discrete event systems in a hierarchical, modular manner. From the simulation result, we can conclude that the proposed architecture conforms the LLRP standard and satisfies all the given functional requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.