Information and Communications Magazine (정보와 통신)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
권호 표지

A Multithreaded Processor Architecture for SDR

  • Published : 2002.11.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper we discuss a multi-threaded baseband Processor capable of executing all physical layer processing of high data rate communications systems completely in software. We discuss the enabling technology for a software defined radio approach and present results for GPRS. 802.11b, and 2Mbps WCDMA. All of these protocols can be executed in real-time on the SB9600 chip using the Sandblaster core.

Keywords

References

  1. http://www.sdrforum.org
  2. M. Saghir, P. Chow, and C. G. Lee. Towards Better DSP Architecture and Compilers, In Proceedings of the International Conference on Signal Processing Applications and Technology, pages 658-664, October, 1994
  3. European Telecommunications Standards Institute, Digital cellular telecommunications system, ANSI-C code for the GSM Enhanced Full Rate (EFR) speech codec (GSM 96.53), March. 1997, ETS 300 724
  4. K.W. Leary and W. Waddington 'DSP/C: A Standard High Level Language for DSP and Numeric Processing', Proceedings of the International Conference on Acoustics, Speech and Signal Processing, IEEE, 1990, pp. 1065-1068
  5. B. Krepp, 'DSP Oriented extensions to ANSI C'. Proceedings of the Inter national Conference on Signal Proc essing Applications and Technology (ICSPAT '97), DSP Associates, 1997 pp. 658-664
  6. D. Batten, S. Jinturkar, J. Glossner, M. Schulte, and P. D' Arcy, 'A New Approach to DSP Intrinsic Functions', Proceedings of the Hawaii International Conference on System Sciences, Hawaii, January, 2000
  7. D. Batten, S. Jinturkar, J. Glossner M. Schulte, R. Peri, and P. D' Arcy, 'Interaction Between Optimizations and a New Type of DSP Intrinsic Function', Proceeding of the International Conference on Signal Processing Applications and Technology (ICSPAT '99), Orlando, Florida November, 1999
  8. A. Aho, R. Sethi, and J. Ullman 'Compilers: Principles. Techniques and Tools', Addison-Wesley Publishing Company, CA, 1986
  9. M. Lam, 'Software Pipelining: An effective scheduling technique for VLIW Machines', In Proceedings of the SIGPLAN '88 Conference on Programming Language Design and Implementation, Atlanta, GA, June, 1988
  10. S. Jinturkar, J. Thilo, J. Glossner, P. D'Arcy, and S. Vassiliadis, 'Profile Directed Compilation in DSP Applications', Proceedings of the Inter- national Conference on Signal Processing Applications and Technology (ICSPAT '98), September, 1998
  11. W. Hwu. 'Super block: An effective technique for VLIW and super-scalar compilation', Journal of Supercomputing, Volume 7, pp.229-248 https://doi.org/10.1007/BF01205185
  12. M. Saghir, P. Chow, and C. G. Lee 'Towards Better DSP Architecture and Compilers', Proceedings of the International Conference on Signal Processing Applications and Technology, October, 1994, pp. 658-664
  13. J. Yoshida, 'Java chip vendors set for cellular skirmish', EE Times, January 30th, 2001
  14. J. Gosling, 'Java Intermediate Bytecodes', ACM SIGNPLAN Workshop on Intermediate Representation (IR95), pp. 111-118, January, 1995
  15. J. Gosling and H. McGilton, 'The Java Language Environment: A White Paper', Sun Microsystems Press, October, 1995
  16. T. Lindholm and F. Yellin, 'Inside the Java Virtual Machine', Unix Review, Vol. 15, No. 1, pp. 31-39, January, 1997
  17. J. Glossner and S. Vassiliadis, 'The Delft Java Engine: An Introduction', Lecture Notes in Computer Science. Third International Euro-Par Conference (Euro-Par '97), pp 776-770, Passau, Germany, August, 1997
  18. J. Glossner and S. Vassiliadis 'Delft Java Dynamic Translation' Proceedings of the 25th EUROMICRO conference (EUROMICRO '99), Milan, Italy, September, 1999
  19. K. Ebcioglu, E. Altman, and E. Hokenek, 'A Java ILP Machine Based on Fast Dynamic Compilation', IEEE MASCOTS International Workshop on Security and Efficiency Aspects of Java. Eilat, Israel, January, 1997