• 제목/요약/키워드: Multi-standard

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HCM 클러스터링과 유전자 알고리즘을 이용한 다중 퍼지 모델 동정 (Identification of Multi-Fuzzy Model by means of HCM Clustering and Genetic Algorithms)

  • 박호성;오성권
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.370-370
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    • 2000
  • In this paper, we design a Multi-Fuzzy model by means of HCM clustering and genetic algorithms for a nonlinear system. In order to determine structure of the proposed Multi-Fuzzy model, HCM clustering method is used. The parameters of membership function of the Multi-Fuzzy ate identified by genetic algorithms. A aggregate performance index with a weighting factor is used to achieve a sound balance between approximation and generalization abilities of the model. We use simplified inference and linear inference as inference method of the proposed Multi-Fuzzy mode] and the standard least square method for estimating consequence parameters of the Multi-Fuzzy. Finally, we use some of numerical data to evaluate the proposed Multi-Fuzzy model and discuss about the usefulness.

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멀티 드롭 멀티 보드 시스템을 위한 새로운 IEEE 1149.1 경계 주사 구조 (New IEEE 1149.1 Boundary Scan Architecture for Multi-drop Multi-board System)

  • 배상민;송동섭;강성호;박영호
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권11호
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    • pp.637-642
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    • 2000
  • IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

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LoRaWAN 통신용 Multi-hop 네트워크 설계에 관한 연구 (A Study on Multi-hop Network Design for LoRaWAN Communication)

  • 김민영;전형구;장종욱
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2019년도 춘계학술대회
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    • pp.129-132
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    • 2019
  • 본 논문은 IoT 제품에서 사용하는 데이터 통신망 중 LoRaWAN Gateway의 Back-haul 사용료 절감 및 통신 커버리지를 확장하기 위해 기존 Single-hop 방식에서 Multi-hop 기반의 네트워크로 설계를 위한 연구 내용 다룬다. 본 본문은 기존 Single-hop 방식으로 구현된 LoRaWAN의 통신방식을 분석하여 Multi-hop 네트워크를 어떻게 설계할 것인지 그리고 LoRaWAN 표준안을 분석하여 Multi-hop 네트워크 설계할 때 반영해야 하는 사안들을 무엇이 있는지 언급할 것이다.

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Zooming Statistics: Inference across scales

  • Hannig, Jan;Marron, J.S.;Riedi, R.H.
    • Journal of the Korean Statistical Society
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    • 제30권2호
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    • pp.327-345
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    • 2001
  • New statistical methods are ended to analyzed data in a multi-scale way. Some multi-scale extensions of stand methods, including novel visualization using dynamic graphics are proposed. These tools are used to explore non-standard structure in internet traffic data.

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하드웨어 DES에 적용한 다중라운드 CPA 분석 (Multi-Round CPA on Hardware DES Implementation)

  • 김민구;한동국;이옥연
    • 전자공학회논문지CI
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    • 제49권3호
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    • pp.74-80
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    • 2012
  • 최근 Nakatsu는 전력파형의 정보가 충분하지 못한 환경에서 분석 성능을 향상 시키는 하드웨어 AES(Advanced Encryption Standard)에 대한 다중 라운드 CPA (Correlation Power Analysis, CPA) 분석기법을 제안하였다. 본 논문에서는 하드웨어로 구현된 DES(Data Encryption Algorithm)에 1라운드와 2 라운드를 분석하여 마스터키를 찾아내는 다중 라운드 CPA 분석 방법을 제안한다. 제안된 다중 라운드 CPA 분석 기법은 DPA Contest에서 제공한 하드웨어 DES 암호 알고리즘의 전력파형을 사용하여 시뮬레이션을 하였다. 그 결과 300개의 전력파형의 정보만으로도 마스터키의 모든 정보를 찾을 수 있었다. 또한 단일라운드 CPA 분석 기법보다 다중라운드 CPA 기법이 더 효과적으로 마스터키를 분석하는 것을 검증하였다.

크로스 롤러 가이드 다단 형상인발 공정설계에 관한 연구 (Process Design of Multi-Stage Shape Drawing Process for Cross Roller Guide)

  • 이상곤;이재은;이태규;이선봉;김병민
    • 한국정밀공학회지
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    • 제26권11호
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    • pp.124-130
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    • 2009
  • In the multi-stage shape drawing process, the most important aspect for the economy is the correct design of the various drawing stage. For most of the products commonly available round or square materials can be used as initial material. However, special products should be pre-rolled. This study proposes a process design method of multi-stage shape drawing process for producing cross roller guide. Firstly, a standard classification of shape drawing process is suggested based on the requirement of pre-rolling process. And a design method is proposed to design the intermediate die shape. The process design method is applied to design the multi-stage shape drawing process for producing cross roller guide. Finally, the effectiveness of the proposed design method is verified by FE-analysis and shape drawing experiment.

Decimation Chain Modeling for Dual-Band Radio Receiver and Its Operation for Continuous Packet Connectivity

  • Park, Chester Sungchung;Park, Sungkyung
    • Journal of information and communication convergence engineering
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    • 제13권4호
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    • pp.235-240
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    • 2015
  • A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

다중경로 페이딩 환경에서 OFDM 시스템을 위한 개선된 다중단계 타이밍 옵셋 추정기법 (An Improved Multi-stage Timing Offset Estimation Scheme for OFDM Systems in Multipath Fading Channel)

  • 박종인;노윤갑;윤석호
    • 한국통신학회논문지
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    • 제36권9C호
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    • pp.589-595
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    • 2011
  • 본 논문에서는 다중경로 페이딩 (multipath fading) 채널 환경에서 직교 주파수 분할 다중 (orthogonal frequency division multiplexing: OFDM) 시스템을 위한 개선된 다중단계 (mu1ti-stage) 타이밍 옵셋 (timing offset) 추정기법을 제안한다. 제안한 기법은 기존의 다중단계 타이밍 옵셋 추정기법이 랜덤한 다중경로 채널 성분에 민감하다는 점을 개선하기 위해 상호 상관함수 샘플 표준편차를 이용한다. 모의실험 결과를 통해 제안한 기법이 기존 기법에 비해 우수한 정추정확률과 (correct estimation probability) 평균제곱오차 (mean square error: MSE) 성능을 가짐을 보인다.

면허기반 주파수 공동 사용을 위한 멀티모드 단말기 설계 및 구현 (Design and Implementation of Multi-mode Mobile Device for supporting License Shared Access)

  • 김용;최승원
    • 디지털산업정보학회논문지
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    • 제12권4호
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    • pp.81-87
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    • 2016
  • Recently, as the heterogeneous network (HetNet) has been deployed widely to support various kinds of Radio Access Networks(RANs) with a combination of Macro, Pico, and/or Femto cells, research and standardization efforts have been very active regarding the concept of Licensed Shared Access (LSA) for supporting spectrum sharing. In order for a mobile device to efficiently support the spectrum sharing, the mobile device shall be reconfigurable, meaning that its radio application code has to be adaptively changed in accordance with the hopping of desired spectral band. Especially, Working Group 2 (WG2) of Technical Committee (TC) Reconfigurable Radio System (RRS) of European Telecommunications Standards Institute (ETSI) has been a main driving force for developing standard architecture for Multi-mode Mobile Device (MD) that can be applied to the LSA system. In this paper, we introduce the Multi-mode MD architecture for supporting LSA-based spectrum sharing. An implementation of a test-bed of Multi-mode MD is presented in order to verify the feasibility of the standard MD architecture for the purpose of LSA-based spectrum sharing through various experimental tests.

Redundant Multi-Valued Logic을 이용한 고속 및 저전력 CMOS Demultiplexer 설계 (Design of a High Speed and Low Power CMOS Demultiplexer Using Redundant Multi-Valued Logic)

  • 김태상;김정범
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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    • pp.148-151
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    • 2005
  • This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

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