• Journal of the Korea Society of Computer and Information
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• v.27 no.1
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• pp.33-41
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• 2022

This paper describes a planar microstrip patch antenna designed on dielectric substrate. Two types of planar microstrip patch antennas are studied for the 5G wireless applications, one type is conventional microstrip structure, the other type is stacked microstrip structure fed by coaxial probe. Using electromagnetically coupling method, stacked microstrip patch antenna employing a multi-layer substrate structure was designed. The results indicate that the proposed stacked microstrip patch antenna performs well at 5G wireless service bandwith a broadband from 3.42GHz to 3.70GHz. The impedance bandwidth(VSWR≤2) is 360MHz(10.28%) from 3.42GHz to 3.78GHz. In this paper, through the designing of a stacked microstrip patch antenna, we have presented the availability for 5G wireless repeater system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.381-382
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• 2007

IZO/Ag/IZO (IAI) anode films for flexible organic light emitting diodes (OLEDs) were grown on PC (polycarbonate) substrate using DC sputter (IZO) and thermal evaporator (Ag) systems as a function of Ag thickness. To investigate electrical and optical properties of IAI stacked films, 4-point probe and UV/Vis spectrometer were used, respectively. From a IAI stacked film with 12nm-thick Ag, sheet resistance of $6.9\;{\Omega}/{\square}$ and transmittance of above 82 % at a range of 500-550 nm wavelength were obtained. In addition, structural and surface properties of IAI stacked films were analyzed by XRD (X-ray diffraction) and SEM (scanning electron microscopy), respectively. Moreover, IAI stacked films showed dramatically improved mechanical properties when subjected to bending both as a function of number of cycles to a fixed radius. Finally, OLEDs fabricated on both flexible IAI stacked anode and conventional ITO/Glass were fabricated and, J-V-L characteristics of those OLEDs were compared by Keithley 2400.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.202-209
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• 2014

In this paper, we analyzed the effects by multi-stacking superstrates over the circular-polarized patch antenna. The previous works considered a single-layered superstrate or a superstrate with multiple layers, and did not almost consider the axial ratio at the performance analysis. First, the effect of center frequency shift is analyzed by the variation of air-gap height between patch antenna and superstrate. The center frequency is down-shifted at the smaller air-gap height and has almost the same frequency as patch antenna at the air-gap height of $005{\lambda}_0$. Second, the antenna performance is analyzed by multi-stacking superstrates with the air-gap height of $005{\lambda}_0$. As the number of multi-stacked superstrates increase, antenna gain has a linear increase and axial ratio is exponentially deteriorated. In addition, it has also been observed that the antenna performance has the same trend with the number of multi-stacked superstrates as the thickness of superstrate increases. Finally, we confirmed that it is possible to design the CP patch antenna with the scalable gain and less than 3dB axial ratio by stacking the superstrate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.781-787
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• 2004

In this paper, a novel dual and wide band aperture stacked patch antenna for Cellular/PCS/IMT-2000 base station is presented. It consists of single microstrip patch having notches along the radiating patch, two dielectric substrates and a form material. To achieve wide band characteristic, we utilize the coupling effect between the notched patch and the resonant aperture in the ground plane and by properly cutting notches on the patch, an aperture stacked patch antenna could be designed to yield dual frequency operation. By the proper choice of resonant aperture size and height of a foam material, dual and wide band characteristic could be realized the measured impedance bandwidth(1:1.5 VSWR) of designed antenna at lower band(860 MHz) reaches 77 MHz and covers the Cellular CDMA band(824∼894 MHz). The measured impedance bandwidth(1:1.5 VSMR) of the designed antenna at upper band(1,960 MHz) is about 550 MHz and covers both the PCS band(1,750∼l,870 MHz) and the for-2000 band(1,920∼2,170 MHz). Good broadside radiation with high gain(5.65∼7.4 dBi) characteristics have also been observed.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.171-175
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• 2004

A tactile stimulator array using stacked PZT is fabricated and evaluated in this paper. The purpose of this research is the development of a tactile stimulator to represent the obstacle information for the visually disabled. As a first step of this research, we investigate the physiological characteristics of tactile stimuli and design a tactile stimulator based on the investigated results. Also we evaluated a fabricated tactile stimulator. The prototype of tactile stimulator which has 2x2 tactor elements with 3mm spacing is fabricated using stacked PZT actuator. In order to evaluate the characteristics of this tactile stimulator, physiological experiments are carried out. In the experiment, the threshold of tactile stimulus intensity within a frequency range of 5-500Hz and at various stimulus amplitudes are investigated. According to the obtained experimental result, the input signal of tactile stimulator for the transfer of obstacle information is determined. Also physiological experiments of multi-stimuli recognition such as shift and rotation are carried out.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.391-396
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• 2023

Recently, as power and electronic devices have increased in frequency and capacity, it has become a major concern to protect electronic circuits and electronic components used in these devices from abnormal voltages such as various surges and pulse noise. To respond to variously rated voltages applied to power electronic devices, the rated voltages of various varistors can be obtained by controlling the size of internal particles of the varistor or controlling the number of layers of the varistor. During bonding, the problem of unbalanced thermal runaway occurring between the electrode and the varistor interface causes degradation of the varistor and shortens its life of the varistor. In this study, to solve the problem of unbalanced heat distribution of stacked varistors to adjust the operating voltage, the contents of the ZnO-based varistor composition were 96 wt% ZnO, 1 mol% Sb₂O₃, 1 mol% Bi₂O₃, 0.5 mol% CoO, 0.5 mol% MnO, and 1 mol% TiO₂. A multi-layered ZnO varistor was modeled by bonding a single varistor with a composition in three layers according to the operating voltage. The thermal distribution of the triple-layered ZnO varistor was analyzed for the thermal runaway phenomenon that occurred during varistor operation using the finite element method according to Comsol 5.2.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.2
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• pp.83-88
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• 2006

AC loss is one of the main research area in AC power application using high temperature superconductor(HTS), such as HTS transformer, HTS current limiter and HTS cable, because it is closely related to efficiency, economic estimation and design of power device. A lot of research for various arrangements of HTS tapes have been performed to increase a capacity of transport current because single HTS tape can not satisfy the demanded current capacity in HTS power application. In this paper, we studied magnetization loss by different several arrangements of BSCCO tapes such as Edge-to-Edge type, Face-to-Face type and Matrix type through numerical analysis by 2D-FEM and measurement. As a result, we got the result that the magnetization loss of Face-to-Face type arrangements was lower than those of other arrangement types under the conditions of the same stacking number. We think that the result was due to shield effect by demagnetization of adjacent HTS tapes which are located face to face.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1796-1802
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• 2024

The production cross sections of ^55,56,57Co, ^52gFe, ^52g,54Mn, ⁵¹Cr, and ⁴⁸V from the ^natFe (p,x) reactions were measured using a proton energy of 57 MeV at the Korea Multi-purpose Accelerator Complex (KOMAC) in Gyeongju, Korea. The conventional stacked-foil activation method and offline γ-ray spectroscopy were used to determine the excitation functions of proton induced nuclear reactions on iron. The measured excitation functions were compared with experimental data in literature and theoretical data from the TENDL-2021 library. The present data show generally good agreement with other experimental data, but discrepancies were found between the present data and the excitation functions of the TENDL-2021 library in the investigated energy range, except for ^56,57Co and ⁵⁴Mn.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.