• Journal of the Korean Society for Precision Engineering
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• v.12 no.5
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• pp.57-68
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• 1995

A general procedure for the numerical solution of coupled, nonlinear, differential two-point boundary-value problems, solutions of which are crucial to the controller design, has been developed and demonstrated. A fixed-end-points, free-terminal-time, optimal-control problem, which is derived from Pontryagin's Maximum Principle, is solved by an extension of Davidenko's method, a differential form of Newton's method, for algebraic root finding. By a discretization process like finite differences, the differential equations are converted to a nonlinear algebraic system. Davidenko's method reconverts this into a pseudo-time-dependent set of implicitly coupled ODEs suitable for solution by modern, high-performance solvers. Another important advantage of Davidenko's method related to the time-optimal problem is that the terminal time can be computed by treating this unkown as an additional variable and sup- plying the Hamiltonian at the terminal time as an additional equation. Davidenko's method uas used to produce optimal trajectories of a single-degree-of-freedom problem. This numerical method provides switching times for open-loop control, minimized terminal time and optimal input torque sequences. This numerical technique could easily be adapted to the multi-point boundary-value problems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.346-349
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• 2013

This paper describes a triple-input energy harvesting circuit using solar, vibration and thermoelectric energy with MPPT(Maximum Power Point Tracking) control. The designed circuit employs MPPT control to harvest maximum power available from a solar cell, PZT vibration element and thermoelectric generator. The harvested energies are simultaneously combined and stored in a storage capacitor, and then managed and transferred into a sensor node by PMU(Power Management Unit). MPPT controls are implemented using the linear relation between the open-circuit voltage of an energy transducer and its MPP(Maximum Power Point) voltage. The proposed circuit is designed in a CMOS 0.18um technology and its functionality has been verified through extensive simulations. The designed chip occupies $945{\mu}m{\times}995{\mu}m$.

• Archives of design research
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• v.12 no.2
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• pp.109-118
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• 1999

Korea adopted a university education ,which it would have been many changes and innovations until modem developed university has its distinct feature. Design education is started just before release of korea and it has inclueded various majors in many changes until now. On the basis of 'Design', multi-media design has been happened and it shows the em of computer. With this change, the School Curriculum was tried many revisions and major subjects has had many changes reflecting the trend of the times. The Visual Communication Design Education is no exception to this. Especially the Visual Communication Design Education has a special quality that accept ail kinds of medium which can deliver on visual angle. Also it takes the problem that how to receive and teach new medium-Computer. The University education that original subject and new computer subject are mixed appropriately must be established promptly. We reside at the very point where past and present merge toward the future of computer graphic design.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• Proceedings of the KOSOMBE Conference
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• v.1991 no.05
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• pp.86-88
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• 1991

A micro-computer based system has been designed to evaluate the performance of infant incubators. The measurement system used a hybrid of analog electronics for amplification, integration and switches and micro-computer for data storage, data display, and control of relay. This approach has been applied to measure the warm-up time, temperature stability, temperature change due to open/close of door and portholes, and temperature distribution on the mattress. The micro-computer provides on-line access of multi-point temperature data.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.459-462
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• 2004

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.210-213
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• 1990

This paper presents the countermeasure to present the main transformer of distribution substation from deteriorating and failing due to repeated magnetic force of the transformer winding by ground fault current in 22.9kV multi grounded distribution system. The Winding strength to the short circuit current is designed to be endurable to the stress of over current. But this design is related to the manufactures. In this paper we examine the application of shunt reactor to the neutral point of the low side of the transformer to reduce fault current due to the fault in the distribution lines we have analysed the fault characteristics of the system and calculated the optimum ohmic values of the neutral reactor.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.65-67
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• 2008

An adaptive response surface method with Latin Hypercube sampling strategy is employed to optimize a magnet pole shape of large scale BLDC motor to minimize the cogging torque. The proposed algorithm consists of the multi-objective Pareto optimization and ($1+{\lambda}$) evolution strategy to find the global optimal points with relatively fewer sampling data. In the adaptive RSM, an adaptive sampling point insertion method is developed utilizing the design sensitivities computed by using finite element method to set a reasonable response surface with a relatively small number of sampling points. The developed algorithm is applied to the shape optimization of PM poles for 6MW BLDC motor.

• Journal of The Korean Digital Architecture Interior Association
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• v.5 no.2
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• pp.15-20
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• 2005

It extended in the opening after simultaneous strong point flag and to Incheon the building where the designer whom the many modem time building comes to build but becomes known was not many so. The research against these people did not become accomplished and not to be the back author research which analyzes the work propensity which is the possibility of doing the possibility of becoming accomplished there was not a basic of architectural design. The research which it sees it led and khu lu thu the road khey keyl the back the depths data, it confronted compared to it secured does not become known during that time the multi architect who and the plan office and and and it searched the result of the back which it puts out well it put to the architects who become known and.