• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.1
• /
• pp.1-8
• /
• 2015

To produce the white light, there are a single chip method using the blue light and phosphor coating, a multi chip method by mixing R, G, B light.. Multi chip method is proper for the smart lighting system by controling color and color temperature. And color rendering of single chip LED is good by even spectral distribution. To apply application technic like smart light system, this paper analyzed the properties of single chip LED and RGB multi chip LED, and implemented the 2 part subject evaluation for single chip LED and RGB multi chip LED. The first part is comparison of properties for single chip LED and RGB multi chip and second part is color appearance evaluation of 8 colors in each lighting environment.

• Design & Manufacturing
• /
• v.6 no.2
• /
• pp.74-78
• /
• 2012

A multi-cavity injection mold system of protein chip for point-of-care with cavity temperature and pressure sensors was proposed in this work. In advance of manufacturing for the multi-cavity injection mold system, a single cavity injection mold system to mold protein chip was considered. Injection molding analysis for the presented system was performed to optimize the process of the molding and suggest guides to design. On the basis of the results for the single cavity system, a multi-cavity injection mold system for protein chip was analyzed, designed and manufactured with cavity temperature and pressure sensors. Results of balanced filling for protein chip models were obtained from the presented mold system.

• Nuclear Engineering and Technology
• /
• v.55 no.3
• /
• pp.1015-1020
• /
• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.19-28
• /
• 1997

This paper presents the design of an SSIC chip for synchronization between main and sub pictures in the multi channel TV system (MUCTS). This chip can resolve problems in MUCTS, such as passing through and vertical jolt phenomena. In addition, this chip rpvivides compatibility for normal/doulble scan, interlace/progressive and normal (4:3)/wide (16:9) systems and has high hjorizontal and vertical resolutions (340) dots and 150 lines). In each mode there are 1 channel, 3 channel, and 4 position display functions. This MUCTS chip including three A/D coverters, a D/A converter and seven line memories was fabricated with one chip by using the $0.8\mu\textrm{m}$ CMOS technology. The application areas of this MUCTS ASIC chip include the wide TV, projection TV and te next generation TV for the DBS (direct broadcast system).

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.1
• /
• pp.43-48
• /
• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.12
• /
• pp.1264-1271
• /
• 2009

In this paper, the chip slot antenna which is used for mobile devices and designed for multi-band is proposed. The proposed antenna is comprised of a chip antenna(10 mm$\times$20 mm$\times$1.27 mm) and a system circuit board(30 mm$\times$60 mm$\times$0.8 mm). The chip slot antenna is mounted on the system circuit board and the end of F-type strip line which is patterned on the chip antenna is connected by a via with a ground plane of the system circuit board. So, a chip antenna radiates effectively the energy by transition between a microstrip line of the system circuit board and a open slot structure of the chip antenna. In the results of proposed antenna, impedance bandwidth of 3:1 VSWR(-6 dB return loss) is 1.98 GHz(1.61~3.59 GHz) and 0.8 GHz(5.2~6 GHz). So, it can cover multi-band of DCS, PCS, UMTS, WLAN. The proposed antenna can be applied to mobile devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.65-72
• /
• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.53 no.3
• /
• pp.129-133
• /
• 2004

As In DS/CDMA(direct sequence code division multiple access) system, the system capacity is limited by multiple access interference(MAI), and self-interference(SI) resulting from the multi-path propagation of the desired user signal. This paper, which the approximated analytic chip waveforms are nearly the same as the computer generated chip waveforms are shown. And then, the BER(Bit Error Rate) performances in CDMA system using the approximated analytic chip waveforms are shown.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.11_12
• /
• pp.629-638
• /
• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.107-112
• /
• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.