• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.405-412
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• 2023

With the development of drone and ICT convergence technology, the use of underwater drones such as leisure underwater drones such as underwater exploration for fishing and industrial drones such as bridge piers is increasing. Existing motor controllers are suitable for aerial drones and these can increase the completeness of underwater drones and their reliability in motor control by developing BLDC motor controllers dedicated to underwater drones. By developing a battery management system (BMS) exclusively for underwater drones, battery stability was ensured by checking the state of charge, checking the state of discharge, adjusting cell balancing, and implementing high/voltage protection functions.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.811-814
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• 2009

The HF band maritime communication is have developing to digital methode that techniques should be readied the automatic link establishment of 1:N by coast station to many ship station. Because can use way by polling simply that communication environment calls particular station wicked fellow HF communication states which is much redundancy times for coast station to set link. In amateur radio particular station selective calling do to be using ALE(Automatic Link Establishment) controller by 1:1 automatic link setting way, but expect 1:N link setting by these way in maritime communication very difficult. That is difficult to avoid collision by traffic overload to induce calling of ship stations. Because HF communication considers channel special quality traffic state radio link should be established, and should be applied automatically secures stability of channel as accommodative at traffic overload. In this paper is studied the new radio protocol by 3 step sequency driving of free access, group free access and polling access using multi-tone in single channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.4
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• pp.527-536
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• 2020

It has been found that an attacker can extract the secret key embedded in a security device and recover the operation instruction using power consumption traces which are some kind of side channel information. Many profiling-based side channel attacks based on a deep learning model such as MLP(Multi-Layer Perceptron) method are recently researched. In this paper, we implemented a disassembler for operation instruction set used in the micro-controller AVR XMEGA128-D4. After measuring the template traces on each instruction, we automatically made the pre-processing process and classified the operation instruction set using a deep learning model CNN. As an experimental result, we showed that all instructions are classified with 87.5% accuracy and some core instructions used frequently in device operation are with 99.6% respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.2
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• pp.97-104
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• 2017

In this paper, we designed and fabricated the multi band Transceiver Assembly(TCA) for the Multi Channel Synthetic Aperture Radar(MCSAR) containing C-band, X-band, Ku-band and we researched to verify electrical performance of TCA. The transceiver consists of transmitters, receivers, signal selection modules for each band, and stability oscillator, frequency synthesizer, controller, power distributor. The transceiver has a receive path selection and bandwidth selection functions in accordance with the operating mode. And the transceiver can transmit and receive all three bands simultaneously, each band has a bandwidth of up to 300 MHz. Final transmission output of transceiver for each band is over 20 dBm to be suitable for driving the T/R module. Receiver bandwidth is selected according to the required function and receiver gain has approximately C-band 52 dB, X-band 50 dB, Ku-band 60 dB, the maximum noise figure of Ku-band V polarization is 4.28 dB in the whole band H, V polarization. As a result of the electrical performance test, a multi-band TCA is satisfied the property requirements of the MCSAR.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.219-230
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• 2009

With the development of broadcasting technology from analogue to interactive digital, the number of TV channels and TV contents provided to audiences is increasing in a rapid speed. In this multi-channel world, it is difficult to adapt to the increase of the TV channel numbers and their contents merely using remote controller to search channels. For these reasons, the EPG system, one of the essential services providing convenience to audiences, is proposed in this paper. Collaborative filtering method with multi-step filtering is used in EPG to recommend contents according to the preference of audience groups with similar preference. To implement our designed TV contents recommendation EPG, we prefer DiTV and use JavaXlet programming based on MHP. The European DVB-MHP specification will be also our domestic standard in DiTV. Finally, the result is verified by OpenMHP emulator.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.353-368
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• 2023

The four wing unmanned aerial vehicle owns the characteristics of small size, light weight, convenient operation and well stability. But it is easily disturbed by external environmental factors during flight with these disadvantages of short endurance and poor attitude solving ability. For solving these problems, a microprocessor based on STM32 chip is designed and the overall development is completed by the resources such as built-in timer and multi-function mode general-purpose input/output provided by the master micro controller unit, together with radio receiver, attitude meter, barometer, electronic speed control and other devices. The unmanned aerial vehicle can be remotely controlled and send radio waves to its corresponding receiver, control the analog level change of its corresponding channel pins. The master control chip can analyze and process the data to send multiple sets pulse signals of pulse width modulation to each electronic speed control. Then the electronic speed control will transform different pulse signals into different sizes of current value to drive the motor located in each direction of the frame to generate different rotational speed and generate lift force. To control the body of the unmanned aerial vehicle, so as to achieve the operator's requirements for attitude control, the PID controller based on Kalman filter is used to achieve quick response time and control accuracy. Test results show that the design is feasible.