• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11A
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• pp.1085-1091
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• 2006

For an experiment in this paper, designed test bed to secure confidentiality of data and safe transmission that Mobile node exchanges in Mobile network. And, For IPsec use that support basically in MIPv6, modeling and experimented IKEv2 protocol that is used for reliable authentication key management and distribution between End Point. When Mobile node handoff in Mobile network, analyzed effect that authentication key re-exchange and limited bandwidth that happen often get in key exchange. And studied about Performance and latency about authentication setting and exchange process that use multi interface. To conclusion, when Mobile node transmits using IPSec, re-authentication of key confirmed that re-setting by limit of bandwidth that existent Mobile network has can be impossible. According to other result, proposed MN's multi interface is expected to minimise key exchange latency by hand-off when transmit IPSec.

• Geophysics and Geophysical Exploration
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• v.21 no.4
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• pp.213-219
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• 2018

In this study, we simulated 3D wave propagation modeling using a Xeon Phi x200 processor and compared the parallel computation performance with that using a Xeon CPU. Unlike the 1st generation Xeon Phi coprocessor codenamed Knights Corner, the 2nd generation x200 Xeon Phi processor requires no additional communication between the internal memory and the main memory since it can run an operating system directly. The Xeon Phi x200 processor can run large-scale computation independently, with the large main memory and the high-bandwidth memory. For comparison of parallel computation, we performed the modeling using the MPI (Message Passing Interface) and OpenMP (Open Multi-Processing) libraries. Numerical examples using the SEG/EAGE salt model demonstrated that we can achieve 2.69 to 3.24 times faster modeling performance using the Xeon Phi with a large number of computational cores and high-bandwidth memory compared to that using the 12-core CPU.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.79-95
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• 2016

In order to improve the Quality-of-Service (QoS) of latency sensitive applications in next-generation cellular networks, multi-path is adopted to transmit packet stream in real-time to achieve high-quality video transmission in heterogeneous wireless networks. However, multi-path also introduces two important challenges: out-of-order issue and reordering delay. In this paper, we propose a new architecture based on Software Defined Network (SDN) for flow aggregation and flow splitting, and then design a Multiple Access Radio Scheduling (MARS) scheme based on relative Round-Trip Time (RTT) measurement. The QoS metrics including end-to-end delay, throughput and the packet out-of-order problem at the receiver have been investigated using the extensive simulation experiments. The performance results show that this SDN architecture coupled with the proposed MARS scheme can reduce the end-to-end delay and the reordering delay time caused by packet out-of-order as well as achieve a better throughput than the existing SMOS and Round-Robin algorithms.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.1
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1030-1036
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• 2006

In this paper, we present two methods of correcting bit errors in constant amplitude multi-code (CAMC) CDMA, which uses the redundant bits only. The first method is a parity-based bit correction with hard-decision, where the received signals despread into n two-dimensional structure with both horizontal parity and vertical parity. Then, an erroneous bit is corrected for each $4{\times}4$ pattern. The second method is a turbo decoding, which is modified from the decoding of a single parity check product code (SPCPC). Experimental results show that, in the second method, the redundant bits in CAMC can be fully used for the error correction and so they are not really a loss of channel bandwidth. Hence, CAMC provides both a low peak-to-average power ratio and robustness to bit errors.

• Journal of IKEEE
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• v.18 no.4
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• pp.612-619
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• 2014

This paper proposes a real-time multi-camera video surveillance system with automatic resolution control using motion detection. In ordinary times, it acquires 4 channels of QVGA images, and it merges them into single VGA image and transmit it. When motion is detected, it automatically increases the resolution of motion-occurring channel to VGA and decreases those of 3 other channels to QQVGA, and then these images are overlaid and transmitted. Thus, it can magnifies and watches the motion-occurring channel while maintaining transmission bandwidth and monitoring all other channels. When it is synthesized with 0.18 um technology, the maximum operating frequency is 110 MHz, which can theoretically support 4 HD cameras.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.211-216
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• 2009

As demands for high-definition television (HDTV) increase, the implementation of real-time decoding of high-definition (HD) video becomes an important issue. The data size for HD video is so large that real-time processing of the data is difficult to implement, especially with software. In order to implement a fast moving picture expert group-2 decoder for HDTV, we compose five scenarios that use parallel processing techniques such as data decomposition, task decomposition, and pipelining. Assuming the multi digital signal processor environments, we analyze each scenario in three aspects: decoding speed, L1 memory size, and bandwidth. By comparing the scenarios, we decide the most suitable cases for different situations. We simulate the scenarios in the dual-core and dual-central processing unit environment by using OpenMP and analyze the simulation results.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.385-389
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• 2009

Multi-hop wireless mesh networks (WMNs) suffer from significant packet losses due to insufficient available bandwidth and high channel error probability. To conquer packet losses, end-to-end (E2E) error control schemes have been proposed. However, in WMNs, E2E error control schemes are not effective in adapting to the time-varying network condition due to large delay. Thus, in this paper, we propose a network-adaptive error control for video streaming over WMNs that flexibly operates E2E and hop-by-hop (HbH) error control according to network condition. Moreover, to provide lightweight support at intermediate nodes for HbH error control, we use path-partition-based adaptation. To verify the proposed scheme, we implement it and evaluate its transport performance through MPEG-2 video streaming over a real IEEE 802.11a-based WMN testbed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.1805-1824
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• 2013

Recently, the use of wireless body area networks (WBAN) has been increasing rapidly in medical healthcare applications. WBANs consist of smart nodes that can be used to sense and transmit vital data such as heart rate, temperature and ECG from a human body to a medical centre. WBANs depend on limited resources such as energy and bandwidth. In order to utilise these resources efficiently, a very well organized medium access control (MAC) protocol must be considered. In this paper, a new, adaptive and energy-efficient MAC protocol, entitled isMAC, is proposed for WBANs. The proposed MAC is based on multi-channel communication and aims to prolong the network lifetime by effectively employing (i) a collision prevention mechanism, (ii) a coordinator node (WCN) selection algorithm and (iii) a transmission power adjustment approach. The isMAC protocol has been developed and modelled, by using OPNET Modeler simulation software. It is based on a networking scenario that requires especially high data rates such as ECG, for performance evaluation purposes. Packet delay, network throughput and energy consumption have been chosen as performance metrics. The comparison between the simulation results of isMAC and classical IEEE 802.15.4 (ZigBee) protocol shows that isMAC significantly outperforms IEEE 802.15.4 in terms of packet delay, throughput and energy consumption.