• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.455-456
• /
• 2008

New CMOS ROM cell is reported in this paper, distinguished from conventional ones in that it can be re-programmed by multi-times. It uses the comparator offset as the physical storage quantity and the MOSFET FN stress effect for offset programming. It demands very low offset for read, and works well in very low voltage. It can become a promising ROM solution for various SoC systems.

• ETRI Journal
• /
• v.37 no.6
• /
• pp.1188-1198
• /
• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• The Journal of the Acoustical Society of Korea
• /
• v.20 no.8
• /
• pp.19-23
• /
• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.752-755
• /
• 1997

In this paper, a scheduling algorithm is proposed for a programmable logic controller(PLC) with remote I/Os, assuming the multi-tasking facilities. Since sequence programs are executed on the application processor and I/O data are transmitted by the network processor concurrently, the proposed algorithm schedules the data transmission as well as the sequence program execution. The suggested algorithm guarantees the bounded WCRT(worst case response time), which is the one third of the WCRT in the absence of scheduling. Computer simulation shows that the algorithm can be easily applied to a real PLC without critical constraints on utilization of resources and inter-relation among tasks.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.38-49
• /
• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.8
• /
• pp.156-164
• /
• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.832-836
• /
• 2015

In this paper, a DC-DC converter is designed for logic process MTP (multi-time programmable) memory IPs using dual program voltage, which are used for analog trimming or storing chip IDs in sensor applications. The DC-DC converter supplies VPP (=5.25V), VNN (=-5.25V), and VNNL ($=2{\cdot}VNN/5$). It uses MOS capacitors and designed with only 3,3V devices. VPP and VNN are configured in two and five stages, respectively. And their pumping currents are $9.17{\mu}A$ and $9.7{\mu}A$, respectively.

• Proceedings of the KIPE Conference
• /
• 2000.07a
• /
• pp.641-644
• /
• 2000

Recently As the performance of the personal computer has been improving rapidly lots of research for the pc-based numerical computer actively progress in an easy repair maintenance and improving the performance with less cost. This paper presents the design using complex programmable logic device(CPLD). The CPU of Motion Controller that function as the real time control of the independent multi-axis motion the error-detect module and external I/O control made use of 80C196KC, In this paper The PC-NC effectively distributed to the load of NCK(numerical computer kernel) and have the advantage of high speed and precision.

• International Journal of Aeronautical and Space Sciences
• /
• v.17 no.4
• /
• pp.467-475
• /
• 2016

Ultrasonic propagation imaging (UPI) has shown great potential for detection of impairments in complex structures and can be used in wide range of non-destructive evaluation and structural health monitoring applications. The software implementation of such algorithms showed a tendency in time-consumption with increment in scan area because the processor shares its resources with a number of programs running at the same time. This issue was addressed by using field programmable gate arrays (FPGA) that is a dedicated processing solution and used for high speed signal processing algorithms. For this purpose, we need an independent and flexible block of logic which can be used with continuously evolvable hardware based on FPGA. In this paper, we developed an FPGA-based ultrasonic propagation imaging system, where FPGA functions for both data acquisition system and real-time ultrasonic signal processing. The developed UPI system using FPGA board provides better cost-effectiveness and resolution than digitizers, and much faster signal processing time than CPU which was tested using basic ultrasonic propagation algorithms such as ultrasonic wave propagation imaging and multi-directional adjacent wave subtraction. Finally, a comparison of results for processing time between a CPU-based UPI system and the novel FPGA-based system were presented to justify the objective of this research.

• Explosives and Blasting
• /
• v.31 no.2
• /
• pp.14-24
• /
• 2013

The most effective way of the rock removing works in the downtown area is to removing rocks by splitting the rock by blasting with small amount of explosives in the hole. However environmental factors not only limit the applications but also increase the forbidden area. As this is a distributed multi-stage blasting method and to reduce vibration by applying the optimized precisioncontrol-blasting method, it is applicable in all situations. The process is to fix the stemming-help plastic sheet to the hole entrance when stemming explosives and insert detonator and explosive primer with same delay time, two or three sets. This method is more efficient in the downtown area where claims and dispute from vibration are expected. This method is easily usable by designing blast pattern even in the area where delay time blasting is difficult after multi-stage explosive stemming due to short length of blast hole (1.2~3.0m) and there is no detonator wire shortage or dead-pressure.