• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.319-324
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• 2005

The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface(SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShoretStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.65-72
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• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.3
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• pp.317-329
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• 1998

In this paper, we have analyzed the packet error probability of DS/CDMA-Trellis Coded QPSK modulation signal with MRC(Maximum Ratio Combining) diversity reception in Rician fading, multi-user interferences and multipath channel. And then we have evaluated the performance and capacity of DS/CDMA-Trellis Coded QPSK system using the MRC diversity reception as a function of direct power to indirect power ratio ($K_R$), the number of diversity branch(M), the number of multi-user(U), PN chip rate(PN), the number of multipath channel($L_P$), and packet length(PL). From the results, we know that the coding gain of DS/CDMA-Trellis Coded QPSK system with 2 branch MRC diversity is about 6 dB against uncoded DS/CDMA BPSK system with 2 branch MRC diversity in Rician fading ($K_R=6dB), 5 multi-user interferences, and 3 multipath channel. And, we know that coded QPSK signal designed for the AWGN channel also perform well on a Rician fading channel with MRC diversity reception. Consequently, we expected that proposed system structure is reliable to the wireless data communication system in Rician fading, multi-user interferences, and multipath channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

• Asian Pacific Journal of Cancer Prevention
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• v.13 no.5
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• pp.1917-1921
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• 2012

Background: Colorectal cancer is one of the leading causes of mortality worldwide. Genome wide analysis studies have identified sequence mutations causing loss-of-function that are associated with disease occurrence and severity. Epigenetic modifications, such DNA methylation, have also been implicated in many cancers but have yet to be examined in the East Asian population of colorectal cancer patients. Methods: Biopsies of tumors and matched non-cancerous tissue types were obtained and genomic DNA was isolated and subjected to the bisulphite conversion method for comparative DNA methylation analysis on the Illumina Infinium HumanMethylation27 BeadChip. Results: Totals of 258 and 74 genes were found to be hyper- and hypo-methylated as compared to the individual's matched control tissue. Interestingly, three genes that exhibited hypermethylation in their promoter regions, CMTM2, ECRG4, and SH3GL3, were shown to be significantly associated with colorectal cancer in previous studies. Using heatmap cluster analysis, eight hypermethylated and 10 hypomethylated genes were identified as significantly differentially methylated genes in the tumour tissues. Conclusions: Genome-wide methylation profiling facilitates rapid and simultaneous analysis of cancerous cells which may help to identify methylation markers with high sensitivity and specificity for diagnosis and prognosis. Our results show the promise of the microarray technology in identification of potential methylation biomarkers for colorectal cancers.

• ETRI Journal
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• v.38 no.3
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• pp.417-424
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• 2016

In this paper, an accurate characterization of a fabricated X-band transmit/receive module is described with the process of generating control data to correct amplitude and phase deviations in an active electronically scanned array antenna unit. In the characterization, quantization errors (from both a digitally controlled attenuator and a phase shifter) are considered using not theoretical values (due to discrete sets of amplitude and phase states) but measured values (of which implementation errors are a part). By using the presented procedure for the characterization, each initial control bit of both the attenuator and the phase shifter is closest to the required value for each array element position. In addition, each compensated control bit for the parasitic cross effect between amplitude and phase control is decided using the same procedure. Reduction of the peak sidelobe level of an array antenna is presented as an example to validate the proposed procedure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1380-1387
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• 2012

The transmit/receive(T/R) module is a key component in the active phased array system. The brick-type T/R module has been widely used and the miniaturization has been an important factor to get the flexibility of the system configuration. For the miniaturization, multi-function chips(MFC) having a common leg configuration are suitable to reduce the number of required MMICs and a high isolation between transmit and receive paths is necessary for the high gain T/R modules. In this work, we propose a bias timing scheme for the compact T/R module and show the optimum timing based on measurements, in order to improve the feed-back path loop problem and the consequent isolation problem of the common leg configuration. We have implemented high power(7 W/channel) and high T/R gain(35 dB transmit and 30 dB receive gains) within the half size($140{\times}80{\times}16mm^3$) of the conventional T/R modules.