• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• International Journal of Automotive Technology
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• v.8 no.3
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• pp.375-382
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• 2007

The multi-driver off-road vehicle drive-line consists of many components, with close connections among them. In order to design and analyze the drive-line efficiently, a modular methodology should be taken. The aim of a modular approach to the modeling of complex systems is to support behavior analysis and simulation in an iterative and thus complex engineering process, by using encapsulated submodels of components and of their interfaces. Multi-driver off-road vehicles are comparatively complicated. The driving-line is an important core part to the vehicle, it has a significant contribution to the performance. Multi-driver off-road vehicles have complex driving-lines, so performance is heavily dependent on the driving-line. A typical off-road vehicle's driving-line system consists of a torque converter, transmission, transfer case and driving-axles, which transfers the power generated by the engine and distributes it effectively to the driving wheels according to the road condition. According to its main function, this paper proposes a modularized approach for design and evaluation of the vehicle's driving-line. It can be used to effectively estimate the performance of the driving-line during the concept design stage. Through an appropriate analysis and assessment method, an optimal design can be reached. This method has been applied to practical vehicle design, it can improve the design efficiency and is convenient to assess and validate the performance of a vehicle, especially of multi-driver off-road vehicles.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.299-302
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• 2004

본 논문은 OCP(Open Core Protocol)에 호환되는 파이프라인 구조를 가진 시스템 버스와 MPEG 시스템에 적합한 메모리 버스를 갖는 계층 구조를 가지는 새로운 동기 세그먼트 버스를 제안한다. 이 구조는 MPEG 시스템의 모바일 제품에 사용되는 영상 데이터 처리를 위한 메모리 인터페이스에 기반을 둔 버스 구조와 Multi-master와 Multi-slave를 사용하여 고성능의 다중 처리를 위한 양방향 다중 버스 구조(bi-direction multiple bus architecture)를 가진다. 효율적인 데이터 처리를 위하여 파이프라인 stage와 결합된 Master와 Slave의 주소번지가 latency를 결정하며, 시스템의 특성에 따라서 IP 코어를 배치하였다. 제안된 버스는 저 전력 구현을 위하여 세그먼트 버스 구조를 가지고, 멀티미디어 SoC 시스템의 성능 저하 없이 다중 작업이 가능한 구조를 갖는다. Wirability를 고려하여 양방향 구조를 채택하였고, Testablility를 위하여 단방향(uni-direction) 구조와 대체 가능하다. 또한, Local arbiter의 수정만으로 Master의 추가가 가능한 확장 구조를 가진다. Latency를 줄이기 위하여 직접 제어 방식과 단순한 구조의 Central arbiter로 구현되었다.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.937-944
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• 2002

The current fast-growing Internet traffic is demanding more and more network capacity. Photonic packet switching offers high-speed, data rate/format transparency, and configurability, which are some of the important characteristics needed in future networks supporting different forms of data. In this paper, we define that optical backbone networks for IP transport consist of optical packet core switches and optical fibers. We propose a multi-link photonic packet switch managing as single media which unifies the whole bandwidth of multiple wavelengths on the optical fiber in the WDM optical networks. The proposed switch uses optical packet memories of output link equally as well as using the WDM buffer. So it cuts down the required number of buffers and realizes of the optical packet memory economically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• The Journal of Korean Academy of Prosthodontics
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• v.46 no.2
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• pp.148-156
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• 2008

Statement of problems: Self-etch adhesives exhibit some clinical benefits such as ease of manipulation and reduced technique-sensitivity. Nevertheless, some concern remains regarding the bonding effectiveness of self-etch adhesives to enamel, in particular when so-called 'mild' self-etch adhesives are employed. This study compared the microtensile bond strengths to ground enamel of the two-step self-etch adhesive Clearfil SE Bond (Kuraray) to the three-step etch-and- rinse adhesive Scotchbond Multi-Purpose (3M ESPE) and the one-step self-etch adhesive iBond (Heraeus Kulzer). Purpose: The purpose of this study was to determine the effect of a preceding phosphoric acid conditioning step on the bonding effectiveness of a two-step self-etch adhesive to ground enamel. Material and methods: The two-step self-etch adhesive Clearfil SE Bond non-etch group, Clearfil SE Bond etch group with prior 35% phosphoric acid etching, and the one-step self-etch adhesive iBond group were used as experimental groups. The three-step etch-and-rinse adhesive Scotchbond Multi-Purpose was used as a control group. The facial surfaces of bovine incisors were divided in four equal parts cruciformly, and randomly distributed into each group. The facial surface of each incisor was ground with 800-grit silicon carbide paper. Each adhesive group was applied according to the manufacturer's instructions to ground enamel, after which the surface was built up using Light-Core (Bisco). After storage in distilled water at $37^{\circ}C$ for 1 week, the restored teeth were sectioned into enamel beams approximately 0.8*0.8mm in cross section using a low speed precision diamond saw (TOPMET Metsaw-LS). After storage in distilled water at $37^{\circ}C$ for 1 month, 3 months, microtensile bond strength evaluations were performed using microspecimens. The microtensile bond strength (MPa) was derived by dividing the imposed force (N) at time of fracture by the bond area ($mm^2$). The mode of failure at the interface was determined with a microscope (Microscope-B nocular, Nikon). The data of microtensile bond strength were statistically analyzed using a one-way ANOVA, followed by Least Significant Difference Post Hoc Test at a significance level of 5%. Results: The mean microtensile bond strength after 1 month of storage showed no statistically significant difference between all adhesive groups (P>0.05). After 3 months of storage, adhesion to ground enamel of iBond was not significantly different from Clearfil SE Bond etch (P>>0.05), while Clearfil SE Bond non-etch and Scotchbond Multi-Purpose demonstrated significantly lower bond strengths (P<0.05), with no significant differences between the two adhesives. Conclusion: In this study the microtensile bond strength to ground enamel of two-step self-etch adhesive Clearfil SE Bond was not significantly different from three-step etch-and-rinse adhesive Scotchbond Multi-Purpose, and prior etching with 35% phosphoric acid significantly increased the bonding effectiveness of Clearfil SE Bond to enamel at 3 months.

• Journal of the Korean Magnetics Society
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• v.20 no.5
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• pp.182-186
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• 2010

Effect of cobalt substitution on the sintering behavior and magnetic properties of a NiZnCu ferrite was studied. $Ni_{0.36-x}Co_xZn_{0.44}Cu_{0.22}Fe_{1.98}O_4(0{\leq}x{\leq}0.04)$ ferrite was fabricated by a solid stat reaction method. It was proposed and experimentally verified that $Co^{2+}$ substituted NiZnCu ferrite was effective on improving the quality factor and magnetic properties of NiZnCu ferrites for multilayer chip inductors. The ferrite was sintered without sintering aids, at $880{\sim}920^{\circ}C$, for 2 h and the initial permeability, quality factor, density, shrinkage, saturation magnetization, and coercivity were also measured. The quality factor (Q) was increased linearly up to x = 0.01 and decreased rapidly over x = 0.01. As the cobalt content increased, the initial permeability and density of the ferrites decreases. The initial permeability of toroidal sample for $Ni_{0.35}Co_{0.01}Zn_{0.44}Cu_{0.22}Fe_{1.98}O_4$ ferrites sintered at $900^{\circ}C$ was 130 at 1 MHz and quality factor was 230.