• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.321-324
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• 2010

There have been lots of researches on a multi-core processor. The enhancement has been performed through parallelization method. Multi-core architecture in the mobile environment has emerged. But, there is a limit to a mobile CPU's performance. GP-GPU(General-Purpose computing on Graphics Processing Units) can improve performance without adding other dedicated hardware. This paper presents the implementation of Inverse Quantization, Inverse DCT and Color Space Conversion module in H.264/AVC decoder using Multi-Core GP-GPU for a mobile environments. The proposed architecture improves approximately 50% of performance when it use all the features.

• Proceedings of the KACD Conference
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• 2008.05a
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• pp.169-176
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• 2008

The purpose of this study was to evaluate the effect of thickness, filling methods and curing methods on the polymerization of dual cured core materials by means of microhardness test. Two dual cured core materials, MultiCore Flow (Ivoclar Vivadent AG, Schaan, Liechtenstein) and Bis-Core (Bisco Inc., Schaumburg, IL, USA) were used in this study. 2 mm (bulky filled), 4 mm (bulky filled), 6 mm (bulky and incrementally filled) and 8 mm (bulky and incrementally filled)-thickness specimens were prepared with light cure or self cure mode. After storage at $37^{\circ}C$ for 24 hours, the Knoop hardness values (KHN) of top and bottom surfaces were measured and the microhardness ratio of top and bottom surfaces was calculated. The data were analyzed using one-way ANOVA and Scheffe multiple comparison test, with ${\alpha}=0.05$. The effect of thickness on the polymerization of dual cured composites showed material specific results. In 2, 4 and 6 mm groups, the KHN of two materials were not affected by thickness. However, in 8 mm group of MultiCore Flow, the KHN of the bottom surface was lower than those of other groups (p < 0.05). The effect of filling methods on the polymerization of dual cured composites was different by their thickness or materials. In 6 mm thickness, there was no significant difference between bulk and incremental filling groups. In 8 mm thickness, Bis-Core showed no significant difference between groups. However, in MultiCore Flow, the microhardness ratio of bulk filling group was lower than that of incremental filling group (p < 0.05). The effect of curing methods on the polymerization of dual cured composites showed material specific results. In Bis-Core, the KHN of dual cured group were higher than those of self cured group at both surfaces (p < 0.05). However, in MultiCore Flow, the results were not similar at both surfaces. At the top surface, dual cured group showed higher KHN than that of self cured group (p < 0.05). However, in the bottom surface, dual cured group showed lower value than that of self cured group (p < 0.05).

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.9-13
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• 2012

In order to overcome the complexity and power problems of superscalar processors, the multi-core architecture has been prevalent recently. Although the execution-driven simulation is wide spread, the trace-driven simulation has speed advantages over the execution-driven simulation. We present a methodology to simulate multi-core architecture using trace-driven simulator. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the cores ranging from 2 to 16 extensively. As a result, the 16-core processor resulted in 4.1 IPC and 13.3 times speed up over single-core processor on the average.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.1-8
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• 2016

We proposed a load unbalancing scheduling method for energy-efficient multi-core embedded systems considering DVFS (Dynamic Voltage/Frequency Scaling) power consumption and task characteristics. It is a new kind of scheduler which combines load balancing and load unbalancing technique. The purpose of the method is to effectively utilize energy without much effect in performance. In this paper, we conduct experiments on energy consumption and performance using the previous load balancing and unbalancing techniques and our proposed technique. The proposed technique reduced energy consumption more than 13.7% when compared to other algorithms. As a result, the proposed technique shows low energy consumption without much decline in the performance and is adequate for energy-efficient multi-core embedded systems.

• Journal of Computing Science and Engineering
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• v.5 no.4
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• pp.283-287
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• 2011

Due to the proliferation of software parallelization on multi-core CPUs, the number of concurrently executing processes is rapidly increasing. Unlike processes running in a server environment, those executing in a multi-core desktop or a multi-core mobile platform have various correlations. Therefore, it is crucial to consider correlations among concurrently running processes. In this paper, we exploit the property that for a given created location in the binary image of the parent process, the average running time of child processes residing in the run-queue differs. We claim that this property can be exploited to improve the overall system performance by running processes that have a relatively short running time before those with a longer running time. Experimental results verified that the running time was actually improved by 11%.

• Journal of Computing Science and Engineering
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• v.5 no.1
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.381-382
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• 2006

The mechanical behaviors of multi-layered foam core sandwich composite were investigated through a 3-point bending test. The sandwich specimens were obtained from sandwich panel consisting of aluminum faces and urethane foam core. Three types of sandwich specimens such as a single structure, a double structure and a triple structure were considered. The span of sandwich specimens were varied from 170mm to 350mm. According to the results, the flexural and shear properties of multi-layered sandwich composite were found to be higher than those of single-layered sandwich composite.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.331-346
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• 2012

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.11a
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• pp.147-148
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• 2015

This paper proposes a tile level rate control for High Efficiency Video Coding (HEVC). The proposed tile level rate control is designed by considering the multi-core platform of tile in HEVC. The proposed tile level rate control allocates the number of bits for each tile based on the predetermined weight generated from the current picture level rate control. According to the experimental results, the proposed tile level rate control for HEVC on multi-core platform loses negligibly the bitrate accuracy about 0.07% on average over the reference software HM-14.0.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.09a
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• pp.13-16
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• 2005

For mass production, usually injection mold has multi-cavity which is filled through geometrical balanced runner system. Despite geometrical balanced runner system, filling imbalances between cavity to cavity have always been observed. These filing imbalances are one of the most significant factors to affect quality of plastic parts when molding plastic parts in multi-cavity injection mold. Filling imbalances are results from non-symmetrical shear rate distribution within melt as it flows through the runner system. It has been possible to decrease filling imbalance by optimizing processing conditions, but it has not completely eliminated this phenomenon during injection molding processing. This paper presents a solution of these filling imbalances through using 'runner core pin'. The runner core pin which is developed in this study creates a symmetrical shear distribution within runner. As a result of using runner core pin, a remarkable improvement in reducing filling imbalance was confirmed.