Browse > Article
http://dx.doi.org/10.7236/JIWIT.2012.12.3.9

A Study of Trace-driven Simulation for Multi-core Processor Architectures  

Lee, Jong-Bok (Dept. of Information and Communications Engineering, Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.12, no.3, 2012 , pp. 9-13 More about this Journal
Abstract
In order to overcome the complexity and power problems of superscalar processors, the multi-core architecture has been prevalent recently. Although the execution-driven simulation is wide spread, the trace-driven simulation has speed advantages over the execution-driven simulation. We present a methodology to simulate multi-core architecture using trace-driven simulator. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the cores ranging from 2 to 16 extensively. As a result, the 16-core processor resulted in 4.1 IPC and 13.3 times speed up over single-core processor on the average.
Keywords
multi-core processor; trace-driven simulation;
Citations & Related Records
연도 인용수 순위
  • Reference
1 P. K. Dubey, G. B. Adams III, and M. J. Flynn, "Instruction Window Size Trade-Offs and Characterization of Program Parallelism," IEEE Transactions on Computers, vol. 43, pp 431-442, Apr. 1994.   DOI
2 D. E. Culler and J. P. Singh, "Parallel Computer Architecture," Morgan Kauffmann Publishers, Inc. Aug. 1998.
3 S. W. Keckler, K. Olukotun, and H. P. Hofsee, "Multicore Processors and Systems," Springer. 2009.
4 T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
5 D. Pham et. al, "The Design and Implementation of a First-Generation CELL processor," ISSCC 2005.
6 D. Genbrugge and L. Eeckhout, "Chip Multiprocessor Design Space Exploration through Statistical Simulation," IEEE Transactions on Computers 58(12), pp.1668-1681, Dec. 2009.   DOI   ScienceOn
7 A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-driven Simulation of Multithreaded Applications," ISPASS, 2011.
8 T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.   DOI   ScienceOn
9 T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, May. 1992, pp.124-134.
10 S. Biswas, et. al, "Multi-Execution : Multicore Caching for Data-Similar Executions," Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 164-173.
11 M. Monchiero, et. al, "How to Simulate 1000 Cores," ACM SIGARCH Computer Architecture News archive, Vol. 37, Issue 2, May 2009, pp. 10-19   DOI