• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.42-46
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• 2019

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.934-941
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• 2000

We measured the electron transport coefficients, the electron drift velocity W and the longitudinal diffusion coefficient $D_{L}$ in the 0.526% and 5.05% $C_{3}F_{8}$-Ar mixtures over the E/N range from 0.01 Td to 100 Td by the double shutter drift tube, and compared the measured results by Hunter et al. with those. We determined the inelastic collision cross sections for the $C_{3}F_{8}$ molecule by the comparison of the present measurements and the calculation of electron transport coefficients in the $C_{3}F_{8}$-Ar mixtures by using a multi-term Boltzmann equation analysis.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.1027-1028
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• 2009

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.10
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• pp.110-118
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• 2007

In multi-hop wireless network, multi-channel makes it possible to enhance network performance because it reduces channel interferences md contentions. Recently several schemes have been proposed in the literatures to use multi-channel. Especially, MCR(Multi channel routing protocol), which utilize hybrid interface assignment, is a prominent routing protocol. MCR uses simple way to change channel but efficiently reduce channel interferences. In this paper, we propose a load-aware channel selection algorithm called LCS that enhances the channel switching algerian used in MCR protocol. In LCS, channel of a node is assigned based on collected information about queue length of neighbors. Moreover this paper evaluates the performance of in by using simulation test and testbed demonstration. Test results show that the MCR with LCS outperforms the naive MCR.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.533-534
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• 2008

By using Dual Port DRAM to Multi-media SoC, an improved performance is achieved in this paper. The proposed scheme greatly help the multi-media SoC like a application for full HDTV, and it can be extended to the application field which is needed the low access latency with heavy traffic. Additionally, the proposed scheme help to down the BUM cost of system.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.3
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• pp.37-43
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• 2007

Recent technological developments in machine tools have been focused on high speed, low vibration machining and high precision machining. And the concern with multi-functional machining has been increased for the last several years. Multi-tasking machines are widely used in machine tool industries. Laser multi-tasking machine has been developed for high precision and fewer vibration machining. The purpose of this study is to evaluate the effects of structural reinforcement on Laser multi-tasking machine which is comprehensively combined turning center and laser machine. Up to date, for the structural stability evaluation of a multi-tasking machine, the analysis model has been considered only the weight of the upper parts. The positions of upper parts on multi-tasking machine have not been considered in the model. So, the results of the present FE model have revealed some difference with measurement data in case of multi-tasking machine. Design of the machine and structural analysis is carried out by FEM simulation using the commercial software CATIA V5. In the result of the structural analysis, effectiveness of reinforcement of the bed was confirmed.