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The Method of Parallel Test Efficiency Improvement using Multi-Clock Mode  

Hong, Chan Eui (Hoseo University, School of Electronics and Display Engineering)
Ahn, Jin-Ho (Hoseo University, School of Electronics and Display Engineering)
Publication Information
Journal of the Semiconductor & Display Technology / v.18, no.3, 2019 , pp. 42-46 More about this Journal
Abstract
In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.
Keywords
Network-On-Chip; Multi-Clock Mode; Parallel Test; ATE; Multi-Site Test;
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