• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.12-22
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• 2000

This paper presents the window-based permit distribution scheme for efficient medium access control to support multiclass traffic in APON(ATM over passive optical network). The proposed MAC protocol considers the characteristics of QoS(Quality of Service) for various traffic classes. A periodic RAU(request access unit) in upstream direction, includes dedicative request fields for each traffic category within the request slot. The transmission of upstream cell is permitted by the proposed window-based spacing scheme which distributes the requested traffic into several segments in the unit of one spacing window. The delay sensitive traffic source such as CBR or VBR with the stringent requirements on CDV and delay, is allocated prior to any other class. In order to reduce the CDV, so that the permit arrival rate close to the cell arrival rate, Running-Window algorithm is applied to permit distribution processing for these classes. The ABR traffic, which has not-strict CDV or delay criteria, is allocated flexibly to the residual bandwidth in FIFO manner. UBR traffic is allocated with the lowest priority for the remaining capacity. The performance of proposed protocol is evaluated in terms of transfer delay and 1-point CDV according to various offered load. The simulation results show that our protocol has the prominent improvement on CDV and delay performance with compared to the previous protocol.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.773-787
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• 2006

An airborne radar is an essential aviation electronic system for the aircraft to perform various civil and/or military missions in all weather environments. This paper presents the design, development, and test results of the multi-mode X-band pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRUs(Line-Replacement Unit), which include antenna unit, transmitter and receiver unit, radar signal & data processing unit and display Unit. The developed core technologies include the planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, MTI, DSP based Doppler FFT filter, adaptive CFAR, moving clutter compensation, platform motion stabilizer, and tracking capability. The design performance of the developed radar system is verified through various ground fixed and moving vehicle test as well as helicopter-borne field tests including MTD(Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

• The Bulletin of The Korean Astronomical Society
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• v.42 no.1
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• pp.32.1-32.1
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• 2017

To dynamically and chemically understand how filaments, dense cores, and stars form under different environments, we are conducting a systematic mapping survey of nearby molecular clouds using the TRAO 14 m telescope with high ($N_2H^+$ 1-0, $HCO^+$ 1-0, SO 32-21, and $NH_2D$ v=1-0) and low ($^{13}CO$ 1-0, $C^{18}O$ 1-0) density tracers. The goals of this survey are to obtain the velocity distribution of low dense filaments and their dense cores for the study of their origin of the formation, to understand whether the dense cores form from any radial accretion or inward motions toward dense cores from their surrounding filaments, and to study the chemical differentiation of the filaments and the dense cores. Until Feb. 2017, the real OTF observation time is 460 hours. We have almost completed mapping observation with four molecular lines ($^{13}CO$ 1-0, $C^{18}O$ 1-0, $N_2H^+$ 1-0, and $HCO^+$ 1-0) on the five regions of molecular clouds (L1251 of Cepheus, Perseus west, Polaris south, BISTRO region of Serpense, California, and Orion B). The maps of a total area of $7.38deg^2$ for both $^{13}CO$ and $C^{18}O$ lines and $2.19deg^2$ for both $N_2H^+$ and $HCO^+$ lines were obtained. All OTF data were regridded to a cell size of 22 by 22 arcseconds. The $^{13}CO$ and $C^{18}O$ data show the RMS noise level of about 0.22 K and $N_2H^+$ and $HCO^+$ data show about 0.14 K at the velocity resolution of 0.06 km/s. Additional observations will be made on some regions that have not reached the noise level for analysis. We are refining the process for a massive amount of data and the data reduction and analysis are underway. This presentation introduces the overall progress from observations to data processing and the initial analysis results to date.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.10
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• pp.36-41
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• 2017

The mobile mapping system first introduced at Ohio State University in 1991 is being developed in various forms as sensor technology develops. The mobile mapping system can acquire geospatial information around amoving object quickly using the information gathered using the position and attitude information of the moving object and the data from various sensors. The mobile mapping system can rapidly acquire large amounts of Geospatial information and MMS provides maximum productivity in the same measurement methods as existing GNSS and total stations. Currently, a variety of systems are being launched, mainly by foreign companies, and they are applied to the construction of geospatial information. On the other hand, the application of domestic technology development or production is insufficient. This paper provides basic data for the introduction of a mobile mapping system to geospatial information related business by conducting the status survey and feature analysis of a commercialized system focusing on the ground-based mobile mapping system. The research identified the current status and characteristics of high-priced, low-priced, indoor, and handheld mobile mapping systems based on vehicles and suggest that the recent system development trends are moving toward lowering the unit prices. The mobile mapping system is currently being developed as a platform for the application of geospatial information construction and the launch of low-cost models. The development of data processing technologies, such as automatic matching and the launch of low-cost models, are forming a basis for the application of mobile mapping systems in the field of geospatial information construction.

• Journal of Broadcast Engineering
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• v.25 no.5
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• pp.750-757
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• 2020

One of the basic tasks for robots to interact with humans is to quickly and accurately grasp human behavior. Therefore, it is necessary to increase the accuracy of human pose recognition when the robot is estimating the human pose and to recognize it as quickly as possible. However, when the human pose is estimated using deep learning, which is a representative method of artificial intelligence technology, recognition accuracy and speed are not satisfied at the same time. Therefore, it is common to select one of a top-down method that has high inference accuracy or a bottom-up method that has high processing speed. In this paper, we propose two methods that complement the disadvantages while including both the advantages of the two methods mentioned above. The first is to perform parallel inference on the server using multi GPU, and the second is to mix bottom-up and One-class Classification. As a result of the experiment, both of the methods presented in this paper showed improvement in speed. If these two methods are applied to the entertainment robot, it is expected that a highly reliable interaction with the audience can be performed.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.374-386
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• 2004

The mammogram provides the way to observe detailed internal organization of breasts to radiologists for the early detection. This paper is mainly focused on efficiently detecting the Microcalcification's Region Of Interest(ROI)s. Breast cancers can be caused from either microcalcifications or masses. Microcalcifications are appeared in a digital mammogram as tiny dots that have a little higher gray levels than their surrounding pixels. We can roughly determine the area which possibly contain microcalifications. In general, it is very challenging to find all the microcalcifications in a digital mammogram, because they are similar to some tissue parts of a breast. To efficiently detect microcalcifications ROI, we used four sequential processes; preprocessing for breast area detection, modified multilevel thresholding, ROI selection using simple thresholding filters and final ROI selection with two stages of neural networks. The filtering process with boundary conditions removes easily-distinguishable tissues while keeping all microcalcifications so that it cleans the thresholded mammogram images and speeds up the later processing by the average of 86％. The first neural network shows the average of 96.66％ recognition rate. The second neural network performs better by showing the average recognition rate 98.26％. By removing all tissues while keeping microcalcifications as much as possible, the next parts of a CAD system for detecting breast cancers can become much simpler.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.