• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.1
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• pp.1-8
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• 2020

The thermal image device support image to detect infrared light from the object without light. It can use not only defence-related industry, but also civilian industry. This paper presents a new thermal image processing module using common image processor. The proposed module shows 10~20% performance improvement with normal mode and 50% performance improvement with sleep mode compared with the previously thermal image module based FPGA. and it guarantees high scalability according to modular system. In addition, the proposed module improves modulation and reuse, so it expect to have reduction of development period, low development cost. various application. In addition, it expect to have satisfaction of customer requirements, development design, development period, release date of product.

• Journal of the Korean Society of Radiology
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• v.14 no.4
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• pp.353-360
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• 2020

This research aims at suggesting exposure condition that shows maintaining the value of the physical image quality factor by decreasing tube voltage and tube current from the standard exposure condition(80 kV, 7 mA) of a CBCT apparatus. To measure the value of the physical image quality factor, modular transfer function(MTF) was analyzed and dose-area product(DAP) was used for the measurement of exposure dose. CBCT images of a Sedentex IQ phantom were obtained under 15 exposure conditions of different combination of tube voltage(80, 78, 76 kV) and tube current(7, 6, 5, 4, 3 mA) and MTF 10 was calculated under each exposure conditions. There were no significant differences in MTF 10 under 80 kV-6 mA, 80 kV-5 mA exposure conditions in comparison with standard exposure condition. Based on the results of this research, 80 kV-5 mA condition are expected to be able to reduce exposure dose with maintaining the value of the physical image quality factor of the standard exposure condition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Nuclear Engineering and Technology
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• v.41 no.6
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• pp.785-796
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• 2009

A KALIMER-600 concept which is a type of sodium-cooled fast reactor, has been developed at KAERI. It uses sodium as a primary coolant and is a pool-type reactor to enhance safety. Also, a supercritical carbon dioxide ($CO_2$) Brayton cycle is considered as an alternative to an energy conversion system to eliminate the sodium water reaction and to improve efficiency. In this study, a simplified model for analyzing the thermodynamic performance of the KALIMER-600 coupled with a supercritical $CO_2$ Brayton cycle was developed. To develop the analysis model, a commercial modular modeling system (MMS) was adopted as a base engine, which was developed by nHance Technology in USA. It has a convenient graphical user interface and many component modules to model the plant. A new user library for thermodynamic properties of sodium and supercritical $CO_2$ was developed and attached to the MMS. In addition, some component modules in the MMS were modified to be appropriate for analysis of the KALIMER-600 coupled with the supercritical $CO_2$ cycle. Then, a simplified performance analysis code was developed by modeling the KALIMER-600 plant with the modified MMS. After evaluating the developed code with each component data and a steady state of the plant, a simple power reduction and recovery event was evaluated. The results showed an achievable capability for a performance analysis code. The developed code will be used to develop the operational strategy and some control logics for the operation of the KALIMER-600 with a supercritical $CO_2$ Brayton cycle after further studies of analyzing various operational events.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.3-11
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• 2011

Evaluation of cube roots in characteristic three finite fields is required for Tate (or modified Tate) pairing computation. The Hamming weights (the number of nonzero coefficients) in the polynomial representations of $x^{1/3}$ and $x^{2/3}$ determine the efficiency of cube roots computation, where $F_{3^m}$is represented as $F_3[x]/(f)$ and $f(x)=x^m+ax^k+b{\in}F_3[x]$ (a, $b{\in}F_3$) is an irreducible trinomial. O. Ahmadi et al. determined the Hamming weights of $x^{1/3}$ and $x^{2/3}$ for all irreducible trinomials. In this paper, we present formulas for cube roots in $F_{3^m}$ using the shifted polynomial basis(SPB). Moreover, we provide the suitable shifted polynomial basis bring no further modular reduction process.

• Korean Journal of Construction Engineering and Management
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• v.24 no.2
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• pp.37-49
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• 2023

In this study, we proposed resource allocation methodologies to improve the productivity of steel bridge manufacturing plants based on the constraint theory which is very popular in the area of manufacturing industries. To this end, after defining the painting process as a bottleneck, three resource allocation methodologies were developed: Operation Specific Resource Allocation (OSRA), Product Specific Resource Allocation (PSRA), and General Resource Allocation (GRA). As a result of experiments for performance evaluation using a simulation model of the steel bridge supply chain, GRA showed the best performance in terms of the Number of Work-In-Process (NWIP) and Waiting Time (WT), in particular, as workload itself and its variability were increased, the performance gap with the specific resource allocation became further deepened. On average, GRA reduced NWIP by 36.2% and WT by 34.6% compared to OSRA, and reduced NWIP by 71.0% and WT by 70.4% compared to PSRA. The reduction of NWIP and WT means alleviating the bottleneck of the painting process, which eventually means that the productivity of the steel bridge manufacturing plant has improved.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.17-28
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• 2024

As listed as one of the most important requirements for Post-Quantum Cryptography standardization process by National Institute of Standards and Technology, the resistance to various side-channel attacks is considered very critical in deploying cryptosystems in practice. In fact, cryptosystems can easily be broken by side-channel attacks, even though they are considered to be secure in the mathematical point of view. The timing attack(TA) and the simple power analysis attack(SPA) are such side-channel attack methods which can reveal sensitive information by analyzing the timing behavior or the power consumption pattern of cryptographic operations. Thus, appropriate measures against such attacks must carefully be considered in the early stage of cryptosystem's implementation process. The Montgomery multiplier is a commonly used and classical gadget in implementing big-number-based cryptosystems including RSA and ECC. And, as recently proposed as an alternative of building blocks for implementing post quantum cryptography such as lattice-based cryptography, the big-number multiplier including the Montgomery multiplier still plays a role in modern cryptography. However, in spite of its effectiveness and wide-adoption, the multiplier is known to be vulnerable to TA and SPA. And this paper proposes a new countermeasure for the Montgomery multiplier against TA and SPA. Briefly speaking, the new measure first represents a multiplication operand without 0 digits, so the resulting multiplication operation behaves in a very regular manner. Also, the new algorithm removes the extra final reduction (which is intrinsic to the modular multiplication) to make the resulting multiplier more timing-independent. Consequently, the resulting multiplier operates in constant time so that it totally removes any TA and SPA vulnerabilities. Since the proposed method can process multi bits at a time, implementers can also trade-off the performance with the resource usage to get desirable implementation characteristics.