• Title/Summary/Keyword: Modified CSD

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Modified CSD Group Multiplier Design for Predetermined Coefficient Groups (그룹 곱셈 계수를 위한 Modified CSD 그룹 곱셈기 디자인)

  • Kim, Yong-Eun;Xu, Yi-Nan;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.48-53
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    • 2007
  • Some digital signal processing applications, such as FFT, request multiplications with a group(or, groups) of a few predetermined coefficients. In this paper, based on the modified CSD algorithm, an efficient multiplier design method for predetermined coefficient groups is proposed. In the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), and in the multiplier design used in 128 point $radix-2^4$ FFT, it is shown that the area, power and delay time can be reduced up to 34%.

Design of Low Error Fixed-Width Group CSD Multiplier (저오차 고정길이 그룹 CSD 곱셈기 설계)

  • Kim, Yong-Eun;Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.33-38
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    • 2009
  • The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

Time-Multiplexed FIR Filter Design Using Group CSD(GCSD) Multipliers (Group CSD(GCSD) 곱셈기를 이용한 Time-Multiplexed FIR 필터 설계)

  • Jeon, Chang-Ha;Seo, Dong-Hyun;Chung, Jin-Gyun;Kim, Yong-Eun;Lee, Chul-Dong
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.452-456
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    • 2010
  • Multiplication is a fundamental arithmetic operation in many digital signal processing (DSP) and communication algorithms. The group CSD (GCSD) multiplier was recently proposed based on the variation of canonical signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In this paper, it is shown that, by exploiting the characteristics of the filter coefficients, GCSD multipliers can be used for the efficient implementation of time-multiplexed FIR filters.

Fabrication of $La_2T_2O_7$ Thin Film by Chemical Solution Deposition (CSD 방법을 이용한 $La_2T_2O_7$ 박막제조)

  • 장승우;우동찬;이희영;정우식
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.11a
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    • pp.339-342
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    • 1998
  • Ferroelectric L $a_2$ $Ti_2$ $O_{7}$(LTO) thin films were prepared by chemical solution deposition processes. Acetylacetone was used as chelating agent and nitric acid was added in the stock solution to control hydrolysis and condensation reaction rate. The LTO thin films were spin-coated on Pt/Ti/ $SiO_2$/(100)Si and Pt/Zr $O_2$/ $SiO_2$/(100)Si substrates. After multiple coating, dried thin films were heat-treated for decomposition of residual organics and crystallization. The role of acetylacetone in Ti iso-propoxide stabilization by possibly substituting $O^{i}$Pr ligand was studied by H-NMR. B site-rich impurity phase, i.e. L $a_4$ $Ti_{9}$ $O_{24}$, was found after annealing, where its appearance was dependent on process temperature indicating the possible reaction with substrate. Dielectric and other relevant electrical properties were measured and the results were compared between modified sol-gel and MOD processes.s.s.

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The Numerical Study on Breakup and Vaporization Process of GDI Spray under High-Temperature and High-Pressure Conditions (고온.고압의 분위기 조건에서 GDI 분무의 분열 및 증발과정에 대한 수치적 연구)

  • 심영삼;황순철;김덕줄
    • Transactions of the Korean Society of Automotive Engineers
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    • v.12 no.3
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    • pp.44-50
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    • 2004
  • The purpose of this study is to improve the prediction ability of the atomization and vaporization processes of GDI spray under high-pressure and high-temperature conditions. Several models have been introduced and compared. The atomization process was modeled using hybrid breakup model that is composed of Conical Sheet Disintegration (CSD) model and Aerodynamically Progressed TAB(APTAB) model. The vaporization process was modeled using Spalding model, modified Spalding model and Abramzon & Sirignano model. Exciplex fluorescence method was used for comparing the calculated with the experimental results. The experiment and calculation were performed at the ambient pressure of 0.5 MPa and 1.0 MPa and the ambient temperature of 473k. Comparison of caldulated and experimental spray characteristics was carried out and Abramzon & Sirignano model and modified Spalding model had the better prediction ability for vaporization process than Spalding model.

A Modified SaA Architecture for the Implementation of a Multiplierless Programmable FIR Filter for Medical Ultrasound Signal Processing (곱셈기가 제거된 의료 초음파 신호처리용 프로그래머블 FIR 필터 구현을 위한 수정된 SaA 구조)

  • Han, Ho-San;Song, Jae-Hee;Kim, Hak-Hyun;Goh, Bang-Young;Song, Tai-Kyong
    • Journal of Biomedical Engineering Research
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    • v.28 no.3
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    • pp.423-428
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    • 2007
  • Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

Low-power Lattice Wave Digital Filter Design Using CPL (CPL을 이용한 저전력 격자 웨이브 디지털 필터의 설계)

  • 김대연;이영중;정진균;정항근
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.10
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    • pp.39-50
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    • 1998
  • Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

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Thermodynamic Properties of Alternatives for R12, R22 and Performances of Refrigerator (R12 및 R22대체냉매의 열역학적 물성치 및 냉동기의 성능비교)

  • Chang, S.D.;Shin, J.Y.;Ro, S.T.
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.5 no.1
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    • pp.73-83
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    • 1993
  • Thermodynamic properties of alternatives for R12 and R22 were estimated and performances of refrigerating cycle using these refrigerants were compared. In this study, we adopt R134a, R22/R142b, R22/R152a, R22/R152a/R124 as alternatives for R12 and R32/R134a for R22. Thermodynamic properties of these refrigerants were estimated using modified CSD equation of state. Cycle simulations of the refrigerating system considering heat source were carried out in order to compare the performance of the system. R134a shows relatively lower COP than R12 but very similar VCR. R22/R142b(50/50 mass fraction), R22/R152a(10/90), R22/R152a/R124(30/25/45) are good for the substitutes of R12 and R32/R134a(30/70) is appropriate for that of R22 in view of COP and VCR.

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Study on the Generation of Inaudible Binary Random Number Using Canonical Signed Digit Coding (표준 부호 디지트 코딩을 이용한 비가청 이진 랜덤 신호 발생에 관한 연구)

  • Nam, MyungWoo;Lee, Young-Seok
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.8 no.4
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    • pp.263-269
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    • 2015
  • Digital watermarking is imperceptible and statistically undetectable information embeds into digital data. Most information in digital audio watermarking schemes have used binary random sequences. The embedded binary random sequence distorts and modifies the original data while it plays a vital role in security. In this paper, a binary random sequence to improve imperceptibility in perceptual region of the human auditory system is proposed. The basic idea of this work is a modification of a binary random sequence according to the frequency analysis of adjacent binary digits that have different signs in the sequence. The canonical signed digit code (CSDC) is also applied to modify a general binary random sequence and the pair-matching function between original and its modified version. In our experiment, frequency characteristics of the proposed binary random sequence was evaluated and analyzed by Bark scale representation of frequency and frequency gains.