• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.123-129
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• 2009

Ubiquitous home is emerging as the future digital home environments that provide various ubiquitous home services like u-Life, u-Health, etc. It is composed of some home appliances and sensors which are connected through wired/wireless network. Ubiquitous home services become aware of user's context with the information gathered from sensors and make home appliances adapt to the current home situation for maximizing user convenience. In these context-aware home environments, it is the one of significant research topics to predict user behaviors in order to proactively control the home environment. In this paper, we propose Multi-Level prediction algorithm for context-aware services in ubiquitous home environment. The algorithm has two phases, prediction and execution. In the first prediction phase, the next location of user is predicted using tree algorithm with information on users, time, location, devices. In the second execution phase, our table matching method decides home appliances to run according to the prediction, device's location, and user requirement. Since usually home appliances operate together rather than separately, our approach introduces the concept of mode service, so that it is possible to control multiple devices as well as a single one. We also devised some scenarios for the conceptual verification and validated our algorithm through simulations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1084-1096
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• 2016

This paper presents method of design and analysis of a high-speed serial interface connector with a data rate of 12.5 Gbps. A high-speed serial interface connector is composed of various material and complex structures. It is very difficult to match the impedance of each discontinuous portion of connector. Therefore, this paper proposes the structure of a connector line that be simplified a connector. In the structure of proposed connector line, this research presents a method for extracting R, L, C and G parameters, analyzing the differential mode impedance, and minimizing the impedance discontinuity using time domain transmissometry and time domain reflectometry. This paper applies the proposed methods in the connector line to the high-speed serial interface connector. The proposed high-speed serial interface connector, which consists of forty-four pins, is analyzed signal transmission characteristics by changing the width and spacing of the four pins. According to the analysis result, as the width of the ground pin increases, the impedance decreases slightly. And as the distance between the ground pin and the signal pin increases, the impedance increases. In addition, as the width of the signal pin increases, the impedance decreases. And as the distance between the signal pin and the signal pin increases, the impedance decreases. The impedance characteristic of initial connector presents ranges from 96 to $139{\Omega}$. Impedance characteristic after applying the structure of proposed connector is shown as a value between 92.6 to $107.5{\Omega}$. This value satisfies the design objective $100{\Omega}{\pm}10%$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.892-899
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• 2016

In this paper, an X-band 50 W internally matched power amplifier is designed and fabricated using an $80{\times}150{\mu}m$ GaN HEMT that is developed by the $0.25{\mu}m$ GaN HEMT process of ETRI. The optimum source and load impedances are experimentally extracted from the loadpull measurement using impedance-transform-prematching circuits, and the transistor performance is predicted. The power performance of the internally matched power amplifier, whose matching circuits are fabricated on a substrate with ${\varepsilon}_r$ of 10.2, is measured under the pulsed mode of $100{\mu}s$ pulse period and 10 % duty cycle, and the best output power of 47.46 dBm(55.5 W) and the power-added efficiency of 46.6 % are obtained at 9.2 GHz. The output power of 47~47.46 dBm(50~55.7 W) is measured in 9.0~9.5 GHz, and the power-added efficiency is measured to be greater than 43 % in 9.0~9.3 GHz and above 36 % in 9.4~9.5 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.2 no.2
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• pp.19-24
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• 1991

This paper propose a new taegeuk shaped directional couper and verify the possibility of high power division rate in those directional coupler through the experiments. We took the taegeuk shaped structure in those proposed directional coupler to utilize a $3\lambda/4$ section of hybrid ring directional coupler actively, and calculated the branch admittances, which satisfied the condition of perfect matching and isolation in the center frequency, by even odd mode analyzing methodes. On the result, we knew that it can be realized a much higher power division rate than reported result in same circuit area within the producible resistance limit in the microstrip line, made the taegeuk shaped directional couplers with 0, 8, 16 dB power split ratio in the 10 GHz frequency using CGP - 502 plate, and confirmed the validity of theory through the experiments.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.806-812
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• 2009

In this paper, the omnidirectional circularly polarized(CP) antenna using arc-shaped mushroom structure with curved branch is proposed. To obtain a vertical polarization and an omnidirectional radiation pattern, the CP antenna uses zeroth-order resonance(ZOR) mode of composite right and left handed(CRLH) transmission line. The horizontal polarization is achieved by the curved branches. Also, the spacing between curved branch and arc-shaped mushroom structure gives the $90^{\circ}$ phase difference between vortical and horizontal polarization. The proposed antenna, therefore, has an omnidirectional CP radiation pattern In the azimuthal plane. The electrical size of the proposed antenna is reduced by 38%, compared with that of the previously presented omnidirectional CP antenna. In addition, the CP antenna is simply designed without $90^{\circ}$ phase shifter and dual feed line. The proposed antenna uses a Bazooka balun for good impedance matching and radiation pattern. To improve 3 dB axial ratio in XY plane, the designed antenna is optimized. After optimization, the measured 3 dB axial ratio in XY plane is observed in $86{\sim}282^{\circ}$.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.107-114
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• 2020

A power amplifier of 2.4 GHz ISM band is designed to implement a transmitter system. High efficiency amplifiers can be implemented as class E or class F amplifiers. This study has designed a 20 W high efficiency class E amplifier that has simple circuit structure in order to utilize for the ISM band application. The impedance matching circuit was designed by class E design theory and circuit simulation. The designed amplifier has the output power of 44.2 dBm and the power added efficiency of 69% at 2.45 GHz. In order to apply 30 dBm input power to the designed power amplifier, voltage controlled oscillator (VCO) and driving amplifier have been fabricated for the input feeding circuit. The measurement of the power amplifier shows 43.2 dBm output and 65% power added efficiency. This study can be applied to the design of power amplifiers for various wireless communication systems such as wireless power transfer, radio jamming device and high power transmitter.