• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• Steel and Composite Structures
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• v.29 no.4
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• pp.451-464
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• 2018

This paper presents some quasi-static tests for 4 mixed columns composed of CFST column and RC column. The seismic performance and failure mode were studied under low-cyclic revised loading. The failure mode was observed under different axial compression ratios. The hysteretic curve and skeleton curve were obtained. The effects of axial compression ratio on yield mechanism, displacement ductility, energy dissipation, stiffness and strength attenuation were analyzed. The results indicate that the failure behavior of CFST-RC mixed column with archaized style is mainly caused by bending failure and accompanied by some shear failure. The axial compression ratio performs a control function on the yielding order of the upper and lower columns. The yielding mechanism has a great influence on the ductility and energy dissipation capacity of specimens. Based on the experiment, finite element analysis was made to further research the seismic performance by ABAQUS software. The variable parameters were stiffness ratio of upper and lower columns, axial compression ratio, yielding strength of steel tube, concrete strength and rebar ratio. The simulation results show that with the increase of stiffness ratio of the upper and lower columns, the bearing capacity and ductility of specimens can correspondingly increase. As the axial compression ratio increases, the ductility of the specimen decreases gradually. The other three parameters both have positive effect on the bearing capacity but have negative effect on the ductility. The results can provide reference for the design and engineering application of mixed column consisted of CFST-RC in Chinese archaized buildings.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.1-4
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• 1995

The most of conventional ultrasonic transducers are constructed to generate either longitudinal or shear waves, but not both of them. We investigated the mechanism of dual mode transducers that generates both of the longitudinal and shear waves simultaneously with a single PZT element. The study has been aimed to find the desired cut by the examining the piezoelectric properties. Theory predicts that a mixed P/S mode transducer can be constructed using a related Z-cut of a PZT ceramics. We studied the performance of a PZT element as a function of its rotation angle so that its efficiency is optimized to excite the two waves equally strongly. The results are verified by checking the impedance variation of the element with Finite Element Methods, and chocking the wave form by pulse-echo test simulation. Based upon the theory a rotated Z-cut was prepared and a transducer were fabricated. Validity of the theory calculation is verified through the

• Journal of IKEEE
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• v.13 no.1
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• pp.19-29
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• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.1
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• pp.149-168
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• 2015

In cognitive radio networks (CRNs), hybrid overlay and underlay sharing transmission mode is an effective technique for improving the efficiency of radio spectrum. Unlike existing works in the literature, where only one secondary user (SU) uses overlay and underlay modes, the different transmission modes should be allocated to different SUs, according to their different quality of services (QoS), to achieve the maximal efficiency of radio spectrum. However, hybrid sharing mode allocation for heterogeneous services is still a challenge in CRNs. In this paper, we propose a new resource allocation method for hybrid sharing transmission mode of overlay and underlay (HySOU), to achieve more potential resources for SUs to access the spectrum without interfering with the primary users. We formulate the HySOU resource allocation as a mixed-integer programming problem to optimize the total system throughput, satisfying heterogeneous QoS. To decrease the algorithm complexity, we divide the problem into two sub-problems: subchannel allocation and power allocation. Cutset is used to achieve the optimal subchannel allocation, and the optimal power allocation is obtained by Lagrangian dual function decomposition and subgradient algorithm. Simulation results show that the proposed algorithm further improves spectrum utilization with a simultaneous fairness guarantee, and the achieved HySOU diversity gain is a satisfactory improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.820-829
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• 2000

In this paper, DSPA(Dynamic Signalling Period Allocation) algorithm that has been proposed by the authors for MAC(Medium Access Control) protocols in W-ATM(Wireless Asynchronous Transfer Mode) is applied to mixed traffic conditions composed of various service classes. We investigate the bandwidth utilization efficiency and quality of service(QoS) fulfillment by the DSPA algorithm used in W-ATM MAC protocols. Simulation results indicate that the DSPA algorithm significantly increases the throughput of the system with the minimum control overhead. Moreover, QoS of each service class is well satisfied by proper and fair channel allocation to different service classes according to their requirements.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.706-710
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• 2008

The substrate bias effect on the current level of SOI-MOSFETs for high temperature operation has been investigated. In this work, we demonstrate the current level of SOI-MOSFETs can be controlled at different temperatures by applying a control bias to the substrate, showing that all current levels below T=150$^{\circ}C$ can be adjusted to a constant current level. 2D numerical simulation results show that substrate bias effectively controls the current conduction; as the substrate bias effectively lower the potential of the channel, inversion carrier generation is effectively controlled and consequently a constant current conduction level is achieved up to T=150$^{\circ}C$. We also demonstrate that the device simulated in this work has same operation at any temperature below T=150$^{\circ}C$ through mixed mode simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.