• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• 대한전자공학회논문지SD
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• 제39권8호
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• pp.24-33
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• 2002

혼성 신호 회로의 설계에 있어 저비용의 고효율 테스트 효율을 보장하기 위해 테스트의 노력은 계속되어 왔다. 특히 테스트를 고려한 BIST(built-in-self-test)설계 방법으로 발전해가고 있는 추세인데, 회로상에서 전체적인 테스트 용이도와 분석에 있어 보다 향상된 방법으로 접근할 수 있고 이러한 시스템에 대해 분석하는데 수월하게 할 수도 있다. 이 논문에서는 효과적인 테스트를 위한 방법을 위해 DC전압과 전압 위상에 대한 BIST를 구현하는 것을 제안하였다. 즉 정상적인 회로와 고장회로에서의 동작에서 전압과 위상의 차이를 검출하는 회로를 하드웨어상으로 구성함으로써 비용과 시간 등을 효과적으로 줄이는 방법을 제안하였다. 실험 결과에서는 기존의 BIST와 비교하여 향상된 것을 나타낸다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• 한국전자파학회논문지
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• 제24권6호
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• pp.661-670
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• 2013

본 논문에서는 고정 주파수 신호와 선형 주파수 변조 신호가 혼합된 연속 위상을 갖는 주기성 혼합 파형에 대한 선형 주파수 변조 파형의 측정 기법을 제시한다. 다양한 신호 파형을 생성하는 주파수 합성기와 송신 신호를 고출력으로 증폭하는 고출력 증폭기로 구성된 소형 레이더 송신기는 연속 위상을 갖는 혼합 파형을 생성한 다. 첫 번째로 위상이 연속적인 신호를 갖는 소형 레이더 송신기의 구성을 요약하고, 선형 주파수 변조 파형의 비정합에 의한 펄스 압축의 왜곡 특성을 고찰한다. 두 번째로 연속 위상을 갖는 혼합 파형에서 선형 주파수 변조 파형을 측정하기 위해 스펙트럼 분석기를 사용한 측정 기법, 신호원 분석기를 사용한 측정 기법 및 RF 혼합기와 위상 변위기를 사용한 새로운 측정 기법을 기술한다. 마지막으로 측정 결과를 적용한 송신 펄스 파형에 대한 수신 신호의 펄스 압축 결과로부터 측정 기법의 정확도를 확인하였다.

• 비파괴검사학회지
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• 제25권3호
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• pp.201-208
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• 2005

In this paper, absolute and differential eddy current signals from various defects in the steam generator tube are numerically predicted and their signal slope characteristics are investigated. The signal changes due to frequency increase are also observed. After studying signal patterns from various defects and frequencies, the analysis of mixed defect signals affected by the presence of a ferromagnetic support plate is attempted. For the signal prediction, axisymmetric finite element modeling is used and this leads us to the slope angle analysis of the signal. Results show that differential signals are useful for locating the position of a defect under the support plate, while absolute signals are easy to presume and interpret even though the effect of support plate is mixed. Combined use of these two types of signals will help us accomplish a more reliable inspection.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 방송공학회논문지
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• 제18권4호
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• pp.535-542
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• 2013

본 논문에서는 고속 및 고인식률의 성능을 갖는 영상인식 엔진 구조를 제안한다. 본 엔진은 2단계의 특징점 추출 및 분류 알고리즘을 수행하여 자동차와 보행자를 인식할 수 있다. 엔진의 인식률을 높이기 위해 HOG 특징점 값과 LBP 특징점 값을 같이 사용하여 알고리즘을 구성하였으며, 처리 속도를 높이기 위해 병렬 구조를 개선하여 하드웨어를 설계하였다. 실험결과를 통해 설계한 엔진이 초당 90프레임의 인식 처리가 가능하며 FPPW $10^{-4}$ 하에서 97.7%의 보행자 인식률을 가짐을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.901-904
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• 2005

Testing of mixed-signal circuit has become a difficult task for test engineers and efficient test solution to these problems are needed. In this paper a new specification-based mixed-signal test method called TSS(Time Slot Specification) using high performance current sensors and a novel test point selection technique without heavy computational overhead are proposed. External output and power nodes are used for test points and accessed by the current sensors in the ATE.

• 제어로봇시스템학회논문지
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• 제22권7호
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.