• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.661-670
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• 2013

In this paper, we propose the measurement techniques of mixed waveform. Mixed waveform has phase-continuous periodic waveform with fixed frequency signal and Linear Frequency Modulation(LFM) signal. This waveform is generated from a compact radar transmitter with frequency synthesizer and high power amplifier. Frequency synthesizer generates various signal waveform with continuos phase and high power amplifier amplify transmitting signal. First, we describe a compact radar transmitter with the phase-continuos signal and then verify the distortion characteristic of pulse compression by the mismatch of LFM waveform. Second, we describe three kinds of measurement techniques for measuring LFM waveform. These techniques include methods using signal analyzer, signal source analyzer and new methods using RF mixer and phase shifter. Finally, we verify the accuracy of the measurement technique from the pulse compression result of receiving signal.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.3
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• pp.201-208
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• 2005

In this paper, absolute and differential eddy current signals from various defects in the steam generator tube are numerically predicted and their signal slope characteristics are investigated. The signal changes due to frequency increase are also observed. After studying signal patterns from various defects and frequencies, the analysis of mixed defect signals affected by the presence of a ferromagnetic support plate is attempted. For the signal prediction, axisymmetric finite element modeling is used and this leads us to the slope angle analysis of the signal. Results show that differential signals are useful for locating the position of a defect under the support plate, while absolute signals are easy to presume and interpret even though the effect of support plate is mixed. Combined use of these two types of signals will help us accomplish a more reliable inspection.

• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• Journal of Broadcast Engineering
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• v.18 no.4
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• pp.535-542
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• 2013

In this paper, we proposed a advanced hardware engine architecture for high speed and high detection rate image recognitions. We adopted the HOG-LBP feature extraction algorithm and more parallelized architecture in order to achieve higher detection rate and high throughput. As a simulation result, the designed engine which can search about 90 frames per second detects 97.7% of pedestrians when false positive per window is $10^{-4}$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.901-904
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• 2005

Testing of mixed-signal circuit has become a difficult task for test engineers and efficient test solution to these problems are needed. In this paper a new specification-based mixed-signal test method called TSS(Time Slot Specification) using high performance current sensors and a novel test point selection technique without heavy computational overhead are proposed. External output and power nodes are used for test points and accessed by the current sensors in the ATE.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.7
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.