• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.75-81
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• 2007

This paper dealt with the design and implementation of an expert system to monitor and diagnose the lightning arresters in GIS substations. The expert system consists of a data acquisition module(DAM) based on microprocessor and diagnostic algorithms. The DAM measures and analyzes several parameters necessary for the arrester diagnosis such as system voltages, leakage current components, and temperatures. Also, it includes an intelligent surge counter which can record the date and tin, the polarity, and the amplitude of surge currents. All the data acquired is transmitted to a remote computer by a low rate wireless network specified in IEEE 802.15.4 to avoid electromagnetic intereference under high voltage and large current environments. The decision-making for the arrester diagnosis completes with a Java Expert System Shell(JESS) which is composed of a knowledge base, an inference engine and a graphic user interface(GUI).

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.27-33
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• 1984

This paper is an experimental gaudy on the digital hardware implementation of the R2-MF Receiver for 32 channel configurations used in signalling systems between ESS. There are many methods to detect MF signal by DSP techniques, but the requirement for MF detection needs not sharp frequency response, needs only decision about some specific frequencies exist or not at discrete frequency sampling points. The hardware used to implement this algorithm is Am 2900 series "bit-slice microprocessor" chips based on the microprogramming techniques for real time signal processing. And we used the additional Z-80A processor chips for the system control and the decision about which is the right MF signal from the detected MF spectrums. Hence we could enhance the flexibilities of the hardware and the software, this leads that this system is well suits for signalling systems used in TDM ESS.n TDM ESS.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.12
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• pp.1079-1085
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• 2012

For precise motion control, S-curve velocity profile is generally used but it has disadvantage of relatively long calculation time for floating-point arithmetics. In this paper, we present a new generating method for velocity profile to reduce delay time of profile generation so that it overcomes such disadvantage and enhances the efficiency of precise motion control. In this approach, the velocity profile is designed based on the gamma correction expression that is generally used in image processing to obtain a smoother movement without any critical jerk. The proposed velocity profile is designed to support both T-curve and S-curve velocity profile. It can generate precise profile by adding an offset to the velocity profile with decimals under floating point that are not counted during gamma correction arithmetic operation. As a result, the operation time is saved and the efficiency is improved. The proposed method is compared with the existing method that generates velocity profile using ring buffer on a 8-bit low-cost MCU. The result shows that the proposed method has no delay in generating driving profile with good accuracy of each cycle velocity. The significance of the proposed method lies in reduction of the operation time without degrading the motion accuracy. Generated driving signal also shows to verify effectiveness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.29-35
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• 2007

Recently, as the demand of mobile multimedia devices increases and T-DMB is started in Korea, the need of research for integration of mobile devices such as cellular phone, navigation, and portable multimedia player becomes higher. In order to integrate mobile devices, it is necessary to support microprocessor with fast speed and various devices with multimedia service. In this paper, we construct Windows CE 5.0 platform whose BSP supports the embedded system board with ARM11 core and various devices and applications. We also implement the DMB device driver which supports busy waiting and interrupt driven I/O techniques, compare their performance, and then suggest the method to efficiently use the resources of embedded system.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.227-232
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• 2010

According to the development of ubiquitous and computer techniques, the application fields of sensor network have been enlarged. We present the design and implementation of sensor node which is the most important component of sensor network techniques in this paper. The proposed sensor node is implemented with 8-bit microprocessor, and temperature and humidity sensing device to gather temperature and humidity data in real world. It achieves low production cost and user convenience, and also has the feature os existing commercial sensor node. Though our experiments, we show that deviation of temperature and humidity are $5^{\circ}C$ and 23.2% respectively, and the proposed sensor node is reliable in real applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2344-2346
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• 2002

A vacuum control system has been developed for using Ethernet Multi Serial Device Severs (EMSDS) for the Pohang Accelerator Laboratory (PAL) storage ring. There are 124 vacuum ion pumps at the storage ring. It was a very important problem to solve the problem how to control such a big number of vacuum pumps distributed around the ring. After discussions, we decided to develop a serial to ethernet interrace device sever that will be mounted in the control system rack. It has a 32-bits microprocessor embedded Linux, 12 ports RS485 (or RS232) slave interface. one channel 10/100BaseTx ethernet host port, one channel UART host port, and 16 Mbytes large memory buffer. These vacuum pumps are connected to Ion-Pump serial controllers, which chop the AC current so as to control the current in the pumps. The EMSDS connect either 100BaseTx or 10BaseT ethernet networks to asynchronous serial ports for communication with serial device. It can simultaneously control up to 12 ion-pump serial controllers. 12 EMSDS are connected to a personal computer (PC) through the network. The PC can automatically control the EMSDS by sending a set of commands through the TCP/IP network. Upon receiving a command from a PC running under Windows2000 through the network, the EMSDS communicate through the stave serial interrace ports to ion-pump controller. We added some software components on the top of EPICS (Experimental Physics and Industrial Control System) toolkit.

• Proceedings of the IEEK Conference
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• summer
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• pp.410-415
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• 2004

Employing knowledge of adaptive possibilities of agents in multi-agents system, we have explored new aspects of distributed modular systems for building ubiquitous heterogeneous robotic systems using intelligent building blocks (I-BLOCKS) [1] as reconfigurable modules. This paper describes early technological approaches related to technical design, experimental developments and evaluation of adaptive processing and information interaction among I-BLOCKS allowing users to easily develop modular robotic systems. The processing technology presented in this paper is embedded inside each $DUPLO^1$ brick by microprocessor as well as selected sensors and actuators in addition. Behaviors of an I-BLOCKS modular structure are defined by the internal processing functionality of each I-Block in such structure and communication capacities between I-BLOCKS. Users of the I-BLOCKS system can easily do 'programming by building' and thereby create specific functionalities of a modular robotic structure of intelligent artefacts without the need to learn and use traditional programming language. From investigating different effects of modern artificial intelligence, I-BLOCKS we have developed might possibly contain potential possibilities for developing modular robotic system with different types of morphology, functionality and behavior. To assess these potential I-BLOCKS possibilities, the paper presents a limited range of different experimental scenarios in which I-BLOCKS have been used to set-up reconfigurable modular robots. The paper also reports briefly about earlier experiments of I-BLOCKS created on users' natural inspiration by a just defined concept of modular artefacts.