• Korean Journal of Computational Design and Engineering
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• v.15 no.5
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• pp.383-392
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• 2010

The purpose of this study is to develop three Judo-doll systems for enhancement of Judo's performance. Traditional Judo training requires a human training partner. Unfortunately it is not always easy to find one. Multifunctional Judo-doll training system has therefore been developed, and is described here. The system consists of a dummy, a power generating mechanism, and kinematic links. The power-generating mechanism generates forces similar to those of a human, by adjusting deadweights and controlling powderbrake's forces. The powderbrake force is controlled by the microprocessor according to the exercise scenario. The kinetic links, which mimic a human training partner's motions, has been developed based on a $Vicon^{TM}$ system's analysis of the movement of human training partners. This mechanism whose name is "L link-wire" consists of L type links, wire, roller, and dead weight. This mechanism generates the force that leads the link to the neutral position regardless the link is pushed or pulled. The lifting mechanism that lifts the doll when the one-armed shoulder throw skill is applied is also developed. A 32-bit microprocessor controls the whole system; it reads the loadcell data, controls the electromagnetic force, and communicates with a PC via Bluetooth. The training history, including loadcell data, date, and training time, is stored in the PC for analysis. This training system can be used to enhance the Judo performance of any self training player.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.365-374
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• 1998

The SHE(Selected Harmonic Elimination) PWM scheme which eliminates specific lower order harmonics can generate h high quality output waveforms in 3-level PWM inverters. However. its application has limited since SHE switching a angles cannot be calculated on-line by a microprocessor-implemented control system. Based on off-line optimization. in which multiple SHE solutions were found and analysed for 2 to 5 switching angles per quarter in the 3-level SHE PWM pattern. this paper presents an algebraic algorithm for an ordinary microprocessor to calculate approximate SHE S switching angles on-line with such high resolution that it makes no practical difference between the accurate and the a approximate SHE switching angles. By employing the variable of the dc-link voltage Vdc' the proposed SHE PWM p pattern can ideally compensate the dc input fluctuation together with selected harmonics eliminated.

• Korean Journal of Food Science and Technology
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• v.21 no.3
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• pp.387-390
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• 1989

Citrus fruit (Citrus unshiu Marc) were stored in the facillity controlled with a microprocessor-based storage controller, and the respiration rate and weight loss of fruits were measured with the infrared gas analyzer and the strain gauge load cell. The storage conditions and measuring intervals were set by the keyboard of personal computer. The interfacing cicuitry between the computer and Z-80 microprocerssor was built with peripheral Interfacing It chips 6821 and 8255. The data measured were saved to a data file for recording and further analysis. When the fresh and bruised fruits were subjected to the storage condition for 4 days at 20 C, the respiration rate of the fresh one showed a stable value of 3-5ml $CO_2/kg$ h throughout the storage period while the bruised one exihibited an abruptly increased rate after 50 hours. And the weight loss recorded about 5% during the storage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.114-123
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• 1985

This is the second part of the four-part paper describing the development of a packet-switched computer network named the cORNET In this paper, following the first par paper that describes the concepts of the KORNET and the development of the network management center (NMC), wc present the design of the KORNET and the development of the network node processor (NNP) The initial configuration of the KORNET consists of three NNP's and one NMC. We have developed each NNP as a microprocessor-based (Mc68000) multiprocessor system, and implemented the NMC using a super-mini computer (Mv/8000) For the KORNET we use the virtual circuit (VC) method as the packet service strategy and the distributed adaptive routing algorithm to adapt efficiently the variation of node and link status. Also, we use a dynamic buffer management algorithm for efficient storage management. Thc hardware of the NNP system has been designed with emphasis on modularity so that it may be expanded esily . Also, the software of the NNP system has been developed according to the CCITT recommendations X.25, X.3, X.28 and X.29.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.2
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• pp.91-98
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• 2012

Power Quality (PQ) signal such as sag, swell, harmonics, and impulsive transients are the major issues in the operations of the power electronics based devices and microprocessor based equipments. The effectiveness of wavelet based denoising techniques and recognizing different power quality events with noise has been presented in this paper. The algorithms involved in the noisy PQ recognition system are the wavelet based denoising and the back propagation neural networks. Also, in order to verify the real-time performances of the noisy PQ recognition systems under the noisy environments, SIL(Software In the Loop) and PIL(Processor In the Loop) were carried out, resulting in the excellent recognition performances.

• Journal of IKEEE
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• v.19 no.3
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• pp.311-318
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• 2015

This dissertation proposes method for development technology of voice and SMS(Short Message Service) alarming system based on modbus protocol. The proposed technology is composed of the following 3 stages; hardware development based on microprocessor, development of input and output driver for modem, mp3 decoder, making modbus protocol stack. In the stage of hardware development based on microprocessor, we develop hardware which receives alarm from modbus master and transmit sms message, play mp3. In the stage of development of input / ouput device driver such as modem, mp3 decoder, we develop program which control each devices. In the stage of making modbus protocol stack, voice and sms alarm system is made for receiving alarm via modbus protocol. To evaluate performance of proposed technology, we issued alarm to voice and sms alarming system on purpose. As a result, response speed of detecting alarm was 10.7ms, communication distance was 1.2Km, operating temperature was from $-25^{\circ}C$ to $70^{\circ}C$, we confirmed supporting modbus protocol. And we verified that proposed voice and sms alarming system in the thesis has a performance to be used as an industrial building alarming system.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.1
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• pp.41-49
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• 2005

Electromyogram (EMG) signal generated by voluntary contraction of muscles is often used in rehabilitation devices because of its distinct output characteristics compared to other bio-signals. This paper proposes a novel EMG-based human-computer interface for electric-powered wheelchair users with motor disabilities by C4 or C5 spine cord injury. User's commands to control the electric-powered wheelchair are represented by shoulder elevation motions, which are recognized by comparing EMG signals acquired from the levator scapulae muscles with a preset double threshold value. The interface commands for controlling the electric-powered wheelchair consist of combinations of left-, right- and both-shoulders elevation motions. To achieve a real-time interface, we implement an EMG processing hardware composed of analog amplifiers, filters, a mean absolute value circuit and a high-speed microprocessor. The experimental results using an implemented real-time hardware and an electric-powered wheelchair showed that the EMG-based human-computer interface is feasible for the users with severe motor disabilities.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.168-171
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• 2003

As vehicles are more intelligent for convenience and safety of drivers, the in-vehicle networking systems and smart modules are essential components for intelligent vehicles. However, for the smart module to widely apply to the IVN systems, two problems are considered as follows. Firstly, because it is very difficult that transducer manufacturers developed the smart module that supports the existing all IVN protocols, the smart module must be independent to the type of networking protocols. Secondly, when the smart module is exchanged due to its failure, it is necessary how the transducer is only exchanged without exchange of the microprocessor and network transceiver. This paper deals with the IEEE 1451 based smart module that describes the digital interface between a network transceiver and sensor module. Finally. efficiency of the IEEE 1451 based smart module was evaluated on the experimental model.