• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.6
• /
• pp.7-16
• /
• 1984

This paper describes the overall procedure of the development of a digital audio response system. It has been developed specifically as an answering system to the inquiries of telephone numbers from subscribers. The system has been realized based on the residual excited linear prediction (RELP) algorithm that incorporates a pitch predictive loop. Its major advantage over other similar systems is that it produces high quality of synthetic speech, although its memory size is relatively small. The hardware which consists of a speech synthesizer, a controller and an I/O part has been constructed using 2900 series bit-slice microprocessors and an INTEL 8085 microprocessor. The system is capable of real time processing, reliable, and adaptable to other applications.

• 제어로봇시스템학회:학술대회논문집
• /
• 1991.10a
• /
• pp.1077-1080
• /
• 1991

It has been recognized as important subject by users that PID-Controllers widely used in industrial processes must be well-tuned, In this paper, We present an automatic tuning method for PID-Controllers which is based on discrete parameter estimation and application of conventional tuning-rules. The method is easy to implement on microprocessor because critical values are obtained by the mathematical computation. Also, it permits quick on-line tuning. Simulation results show that most processes are well tuned by the suggested tuning method in this paper.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.263-264
• /
• 2006

On this study the performance of engineering workstation running OpenGL based application The following instructions are enhanced by configuring of the microprocessor and main memories. Single processors and more main memories are better than dual and less or same is confirmed.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.6
• /
• pp.879-885
• /
• 1990

The geometrical algorithm for generating a 3-phase SPWM signal for VVVF (Variable Voltage, Variable Frequency) inverter drives is proposed. In this techniques, it is suitable for micro-processor based implementation since the pulsewiths are computable in real time from simple analytic expressions. System hardware consists of the inverter circuit and the 3-phase SPWM signal generating circuit. The inverter circuit is a 3-phase SPWM signal generating circuit is single board micro-processor consisting of Z-80A CPU, EPROMXI, CTC, PIO. The method of controlling VVVF at the inverter output is discussed here.

• Proceedings of the KIEE Conference
• /
• 1987.11a
• /
• pp.543-546
• /
• 1987

Trapezoidal wave is suitable for the modulating signal of the microcomputer based PWM inverter for the use of motor drives because the switching patterns can be generated by means of on-line computation. In this paper, the output waveform of three-level modulation inverters for the trapezoidal modulating signal is investigated both theoretically and experimentally.

• Journal of information and communication convergence engineering
• /
• v.9 no.4
• /
• pp.428-430
• /
• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• ETRI Journal
• /
• v.25 no.5
• /
• pp.337-344
• /
• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.10C
• /
• pp.798-804
• /
• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• Journal of the Korea Society for Simulation
• /
• v.15 no.4
• /
• pp.51-58
• /
• 2006

Debugging embedded softwares is very different from debugging general softwares. For examples, debugging embedded software requires more information, such as information on power consumption, information on the distribution of executed instructions, information on the distribution of used registers, and information on the amount of clocks consumed during the execution of a program, that is not needed in debugging general softwares. In this paper, we propose more effective method fer debugging embedded softwares using an instruction set simulator for the microprocessor that is executing embedded softwares. In this research, we develop a debugger based on an instruction set simulator for a domestic embedded microprocessor called SE1608 and we shows an effective debugging method using a MiBench program which is widely used to benchmark embedded softwares. The debugging method proposed in this paper is relatively easy to implement and shows many advantages compared with existing debugging methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.05a
• /
• pp.295-297
• /
• 2021

In this study, the difference in resilience was analyzed based on the results of the microprocessor class for the group who temporarily conducted online learning due to COVID-19 and made a cross-school course. As a result of the study, the resilience value in online learning was found to be less than 150 in 12, 150 to less than 180 in 33, and 180 or more in 10. On the other hand, the resilience value in offline learning was found to be less than 150, 8 people, 150 or more, 180, 30, 180 or more, 17. Therefore, in subjects that teach hardware and software at the same time, such as a microprocessor, it is necessary to proceed with offline learning that can establish a laboratory learning environment, and when proceeding with online learning unavoidably due to COVID-19, the theory is the same as other theoretical subjects. Content should be focused on.