• Journal of Welding and Joining
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• 제32권3호
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• pp.68-73
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• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.127-133
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• 2001

솔더볼의 피로강도에 대한 솔더 조성의 영향을 조사하기 위하여 패키지 신뢰성 시험을 실시하였다. 공정조성 솔더, S $n_{62}$P $b_{36}$A $g_2$, S $n_{63}$P $b_{34.5}$A $g_2$S $b_{0.5}$ 솔더를 사용해 제조된 시편을 MRT Lv 2a 조건에서 전처리 후 TC 시험을 수행하였다. 제조 직후, 전처리 후, TC 후 각각에 대하여 전단강도를 측정하였으며, 미세 조직 사진을 얻었다. 또한, SEM과 EDX를 이용하여 파괴 기구에 대한 분석을 실시하였으며, 신뢰성 시험 후 전단강도의 저하에 대하여 논의하였다.다.

• 마이크로전자및패키징학회지
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• 제31권3호
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• pp.62-66
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• 2024

초록 본 논문은 경면반사특성을 갖는 마이크로솔더볼의 품질확보를 위한 3차원형상의 결함검사 수단으로서, 정밀한 위치제어장치없이 유리접시에 임의로 놓여있는 마이크로솔더볼의 반사영상을 취득하고 이를 통계적으로 분석하여 3차원 형상의 결함유무를 검사하는 방법을 제안한다. 또한, 마이크로솔더볼에 인위적인 진동을 인가하여 위치와 방향을 바꾸면서 촬영과 검사를 반복하여 결함을 검출하는 방법을 제시하여, 마이크로솔더볼의 일부분만이 보이는 촬영영상의 한계를 극복하였다. 이를 위해 복수개의 LED를 링형태로 배열한 광원을 사용하고, 유리접시에 위치한 많은 수의 마이크로솔더볼을 동시에 촬영한 영상을 취득하고, 영상처리를 통해 반사되는 LED의 상대적 위치를 구한 후, 통계적 분석을 통하여 결함의 유무를 판단하는 방법을 제안하고 실험을 통해 그 효용성을 보인다.

• 마이크로전자및패키징학회지
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• 제28권4호
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• pp.19-23
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• 2021

본 논문은 경면반사특성을 갖는 솔더볼의 생산공정 관리와 품질확보를 목적으로 머신비전을 적용한 3차원형상을 결함검사방법으로서, 60미크론 이내의 마이크로 솔더볼을 대상으로 정밀한 위치제어장치가 필요없이 임의로 위치한 솔더볼의 반사영상을 취득 후 통계적으로 분석하여 3차원 형상의 결함유무를 검사하는 방법을 제안한다. 이를 위해 복수개의 LED를 링형태로 배열한 광원을 사용하여 트레이에 위치한 많은 수의 마이크로솔더볼을 동시에 촬영한 영상을 취득하고, 영상처리를 통해 반사되는 LED의 상대적 위치를 구한 후, 통계적 분석을 통하여 결함의 유무를 판단하는 방법을 제안하고 실험을 통해 그 효용성을 보인다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.80-80
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• 2000

• 한국레이저가공학회:학술대회논문집
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• 한국레이저가공학회 2005년도 춘계학술발표대회 논문집
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• pp.130-139
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• 2005

• Journal of Welding and Joining
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• 제21권4호
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• pp.25-30
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• 2003

There have been many researches for small scale packages such as CSP, BGA, and Flipchip. Underfill encapsulant technology is one of the latest assembly technologies. The underfill encapsulant could enhance the reliability of the packages by flowing into the gap between die and substrate. In this paper, the effects of underfill packages by both aspects of thermal and mechanical reliabilities are studied. Especially, it is focused to value board-level reliability whether by the underfill is applied or not. First of all, The predicted thermal fatigue lifes of underfilled and no underfilled $\mu$ BGA solder joints are performed by Coffin-Manson's equation and FEA program, ANSYS(version 5.62). Also, the thermal fatigue lifes of $\mu$ BGA solder joints are experimented by thermal cycle test during the temperature, 218K to 423k. Consequently, both experimental and numerical study show that $\mu$ BGA with underfill has over ten times better fatigue lift than $\mu$ BGA without underfill.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.481-486
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• 2010

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.