• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.175-177
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• 2002

This paper presents a methodology for analyzing individual differences on Kansei evaluation for a set of product samples. This analysis divides subjects into several groups by each subject's Kansei evaluation data according to what kinds of Kansei are related on what kinds of design elements. The basic idea is to classify the results of cluster analysis in individual subject's ranges. A similarity matrix of subject is computed by comparing dendrogram of each subjects. The methodology is applied to analyzing evaluation data of cellular phone design.

• Journal of the Korean Geotechnical Society
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• v.21 no.9
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• pp.25-34
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• 2005

This paper proposes a selection methodology composed of neural network (NN) and genetic algorithm (GA) to design optimal NN structure. We combine the characteristics of GA and NN to reduce the computational complexity of artificial intelligence applications and increase the precision of NN' prediction in the design of NN structure. Genetic selection approach of design parameters of NN is introduced to obtain optimal NN structure. Analyzed results for geotechnical problems are given to evaluate the performance of the proposed hybrid methodology.

• Computers and Concrete
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• v.30 no.2
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• pp.127-141
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• 2022

In this paper, a numerical procedure is proposed for achieving the minimum cost design of reinforced concrete polygonal column cross-sections under compression and biaxial bending. A methodology is developed to integrate the metaheuristic algorithm Quantum Particle Swarm Optimization (QPSO) with an algorithm for the evaluation of the strength of reinforced concrete cross-sections under combined axial load and biaxial bending, according to the design criteria of Brazilian Standard ABNT NBR 6118:2014. The objective function formulation takes into account the costs of concrete, reinforcement, and formwork. The cross-section dimensions, the number and diameter of rebar and the concrete strength are taken as discrete design variables. This methodology is applied to polygonal cross-sections, such as rectangular sections, rectangular hollow sections, and L-shaped cross-sections. To evaluate the efficiency of the methodology, the optimal solutions obtained were compared to results reported by other authors using conventional methods or alternative optimization techniques. An additional study investigates the effect on final costs for an alternative parametrization of rebar positioning on the cross-section. The proposed optimization method proved to be efficient in the search for optimal solutions, presenting consistent results that confirm the importance of using optimization techniques in the design of reinforced concrete structures.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2006.04a
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• pp.200-207
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• 2006

A new formal standardization methodology of the structural design document information is proposed in this paper. The standardization process is divided into three steps: pre-process of the collected sample document (CSD), construction of the document structure, and definition of the occurrence of each element in the document. During the pre-process, the detail document contents in the CSD are indexed with templates defined in this study, and the indexed CSD is translated into XML Schema (XSD) formal Afterwards the degree of confidences of all elements between the temporary standard document (TSD) and the translated CSD are calculated by using the XML schema matching algorithm; the TSD is then updated. This second step is repeated until all of the CSD are compared. In the final step, the common elements and unbounded elements are extracted by determining the occurrence of the temporary document elements, and the standardized document schema is exported in the XSD format. The case study dealing with the structural calculation documents show that the ,proposed methodology can be effectively used to build a XML -based information model of structural design documents.

• The Journal of Korean Association of Computer Education
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• v.5 no.4
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• pp.31-42
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• 2002

In this paper, We set up the development methodology of communication protocols as well as the concrete design concept concerning for how to define and use the PDU, SDU, SAP, and service primitives using SDL, which is recommended by ITU-T, and other international standard languages such as ASN.l, MSC, and TTCN. This methodology covers the SDL design of extended lures protocol, a well known protocol example, insertion of ASN.1 message for transportation of bit string, generation of MSC for validation of design specification, generation of test cases using TTCN from validation, and performance of conformance test.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.579-584
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• 2003

Solenoid type magnetic actuator is the device, which could translate the electromagnetic energy to mechanical force. The force generated by magnetic flux, could be calculated by Maxwell stress tensor method. Maxwell stress tensor method is influenced by the magnetic flux path. Thus, magnetic force could be improved by modification of the iron case, which is the route of the magnetic flux. Modified design is obtained by parameter optimization using by Response surface methodology.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.357-360
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• 2001

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.