• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.55.1-55.1
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• 2011

Dye-sensitized solar cell(DSSC) have been considered one of the promising alternatives to conventional solar cells, because of their low cost, easy fabrication and relatively high energy conversion efficiency. However, although the cell offers reasonable efficiency at least 11%, the use of a liquid electrolyte placed technological challenges for achieving the desired durability and operational stability of the cell. In order to prevent or reduce electrolyte leakage considerable efforts have been made, such as p-type semiconductor or organic hole-transport material that better mechanical properties and simple fabrication processes. In this work, we synthesized solid-state electrolyte containing LiI and KI metal salt with starting materials of poly ethylene oxide to substitute liquid electrolyte enhance the ionic conductivity and solar conversion efficiency. Li+ leads to faster diffusion and higher efficiency and K+ leading to higher ionic conductivity. The efficiency of poly ethylene oxide/LiI system electrolyte is 1.47% and poly ethylene oxide/potassium electrolyte is 1.21%. An efficiency of 3.24% is achieved using solid-state electrolyte containing LiI and KI concentrations. The increased solar conversion efficiency is attributed to decreased crystallinity in the polymer that leads to enhanced charge transfer.

• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• Korean Journal of Materials Research
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• v.32 no.11
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• pp.458-465
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• 2022

Interest in the use of semiconductor-based photocatalyst materials for the degradation of organic pollutants in a liquid phase has grown, due to their excellent performance and response to the light source. Herein, we fabricated a NiO-SiC-TiO₂ ternary structured photocatalyst which had reduced bandgap energy, with strong activation under UV-light irradiation. The synthesized samples were examined using XRD, SEM, EDX, TEM, DRS, EIS techniques and photocurrent measurement. The results confirmed that the two types of metal oxides were well bonded to the SiC fiber surface. The junction of the new photocatalyst exhibited a large number of photoexcited electrons and holes. The holes tended to oxidize the water and form a hydroxyl radical, which promoted the decomposition of methylene blue. The close contact between the 2D SiC fiber and metal oxide semiconductors expanded the scope of absorption wavelength, and enhanced the usability of the ternary photocatalyst for the degradation of methylene blue. Among three synthesized samples, the NiO-SiC-TiO₂ showed the best photocatalytic effect, and was considered to have excellent photoelectron transfer due to the synergy effect between the metal oxide and SiC.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Safety and Health at Work
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• v.12 no.3
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• pp.403-415
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• 2021

Background: This study aimed to assess the possibility of benzene exposure in workers of a Korean semiconductor manufacturing company by reviewing the issued patents. Methods: A systematic patent search was conducted with the Google "Advanced Patent Search" engine using the keywords "semiconductor" and "benzene" combined with all of the words accessed on January 24, 2016. Results: As a result of the search, we reviewed 75 patent documents filed by a Korean semiconductor manufacturing company from 1994 to 2010. From 22 patents, we found that benzene could have been used as one of the carbon sources in chemical vapor deposition for capacitor; as diamond-like carbon for solar cell, graphene formation, or etching for transition metal thin film; and as a solvent for dielectric film, silicon oxide layer, nanomaterials, photoresist, rise for immersion lithography, electrophotography, and quantum dot ink. Conclusion: Considering the date of patent filing, it is possible that workers in the chemical vapor deposition, immersion lithography, and graphene formation processes could be exposed to benzene from 1996 to 2010.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.347-350
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• 2013

By inserting a very thin metal layer of Ag between two outer oxide layers of amorphous silicon indium zinc oxide (SIZO), we fabricated a highly transparent SIZO/Ag/SIZO multilayer on a glass substrate. In order to find the optimized thickness of Ag layers, we investigated the variation of optical properties depending on Ag thickness. It was found that the transition of Ag layer from island formation to a continuous film occurred at a critical thickness. Continuity of the Ag film is very important for optical properties in SIZO/Ag/SIZO multilayer. With about 15 nm thick Ag layer, the multilayer showed a high optical transmittance of 80% at 550 nm and low emissivity in IR.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP nprocess, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.189-192
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• 2001

Recently, STI process is getting attention as a necessary technology for making high density of semiconductor by devices isolation method. However, it does have various problems caused by CMP process, such as torn oxide defects, nitride residues on oxide, damages of si active region, contaminations due to post-CMP cleaning, difficulty of accurate end point detection in CMP process, etc. In this work, the various defects induced by CMP process was introduced and the above mentioned Problems of CMP process was examined in detail. Finally, the guideline of future CMP process was presented to reduce the effects of these defects.