• 제목/요약/키워드: Metal oxide semiconductor

검색결과 720건 처리시간 0.028초

Complementary FET로 열어가는 반도체 미래 기술 (Complementary FET-The Future of the Semiconductor Transistor)

  • 김상훈;이성현;이왕주;박정우;서동우
    • 전자통신동향분석
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    • 제38권6호
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    • pp.52-61
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    • 2023
  • With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

산화막의 질화, 재산화에 의한 계면트랩밀도 특성 변화 (Characteristics Variation of Oxide Interface Trap Density by Themal Nitridation and Reoxidation)

  • 백도현;이용재
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 1999년도 춘계종합학술대회
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    • pp.411-414
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    • 1999
  • 70 ${\AA}$-thick oxides nitridied at various conditions were reoxidized at pemperatures of 900$^{\circ}C$ in dry-O$_2$ ambients for 5~40 mininutes. The gate oxide interface porperties as well as the oxide substrate interface properties of MOS(Metal Oxide Semiconductor) capacitors with various nitridation conditions, reoxidation conditions and pure oxidation condition were investigated. We stuided I$\sub$g/-V$\sub$g/ characteristics, $\Delta$V$\sub$g/ shift under constant current stress from electrical characteristics point of view and breakdown voltage from leakage current point of view of MOS capacitors with SiO$_2$, NO, RNO dielectrics. Overall, our experimental results show that reoxidized nitrided oxides show inproved charge trapping porperites, I$\sub$g/-V$\sub$g/ characteristics and gate $\Delta$V$\sub$g/ shift. It has also been shown that reoxidized nitridied oxide's leakage currented voltage is better than pure oxide's or nitrided oxide's from leakage current(1${\mu}$A) point of view.

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PD-SOI기판에 제작된 SiGe p-MOSFET의 신뢰성 분석 (Reliability Analysis of SiGe pMOSFETs Formed on PD-SOI)

  • 최상식;최아람;김재연;양전욱;한태현;조덕호;황용우;심규환
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.533-533
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    • 2007
  • The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

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Power Generating Characteristics of Zinc Oxide Nanorods Grown on a Flexible Substrate by a Hydrothermal Method

  • Choi, Jae-Hoon;You, Xueqiu;Kim, Chul;Park, Jung-Il;Pak, James Jung-Ho
    • Journal of Electrical Engineering and Technology
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    • 제5권4호
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    • pp.640-645
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    • 2010
  • This paper describes the power generating property of hydrothermally grown ZnO nanorods on a flexible polyethersulfone (PES) substrate. The piezoelectric currents generated by the ZnO nanorods were measured when bending the ZnO nanorod by using I-AFM, and the measured piezoelectric currents ranged from 60 to 100 pA. When the PtIr coated tip bends a ZnO nanorod, piezoelectrical asymmetric potential is created on the nanorod surface. The Schottky barrier at the ZnO-metal interface accumulates elecntrons and then release very quickly generating the currents when the tip moves from tensile to compressed part of ZnO nanorod. These ZnO nanorods were grown almost vertically with the length of 300-500 nm and the diameter of 30-60 nm on the Ag/Ti/PES substrate at $90^{\circ}C$ for 6 hours by hydrothermal method. The metal-semiconductor interface property was evaluated by using a HP 4145B Semiconductor Parameter Analyzer and the piezoelectric effect of the ZnO nanorods were evaluated by using an I-AFM. From the measured I-V characteristics, it was observed that ZnO-Ag and ZnO-Au metal-semiconductor interfaces showed an ohmic and a Schottky contact characteristics, respectively. ANSYS finite element simulation was performed in order to understand the power generation mechanism of the ZnO nanorods under applied external stress theoretically.

Boosting up the photoconductivity and relaxation time using a double layered indium-zinc-oxide/indium-gallium-zinc-oxide active layer for optical memory devices

  • Lee, Minkyung;Jaisutti, Rawat;Kim, Yong-Hoon
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.278-278
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    • 2016
  • Solution-processed metal-oxide semiconductors have been considered as the next generation semiconducting materials for transparent and flexible electronics due to their high electrical performance. Moreover, since the oxide semiconductors show high sensitivity to light illumination and possess persistent photoconductivity (PPC), these properties can be utilized in realizing optical memory devices, which can transport information much faster than the electrons. In previous works, metal-oxide semiconductors are utilized as a memory device by using the light (i.e. illumination does the "writing", no-gate bias recovery the "reading" operations) [1]. The key issues for realizing the optical memory devices is to have high photoconductivity and a long life time of free electrons in the oxide semiconductors. However, mono-layered indium-zinc-oxide (IZO) and mono-layered indium-gallium-zinc-oxide (IGZO) have limited photoconductivity and relaxation time of 570 nA, 122 sec, 190 nA and 53 sec, respectively. Here, we boosted up the photoconductivity and relaxation time using a double-layered IZO/IGZO active layer structure. Solution-processed IZO (top) and IGZO (bottom) layers are prepared on a Si/SiO2 wafer and we utilized the conventional thermal annealing method. To investigate the photoconductivity and relaxation time, we exposed 9 mW/cm2 intensity light for 30 sec and the decaying behaviors were evaluated. It was found that the double-layered IZO/IGZO showed high photoconductivity and relaxation time of 28 uA and 1048 sec.

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Photo-induced Electrical Properties of Metal-oxide Nanocrystal Memory Devices

  • Lee, Dong-Uk;Cho, Seong-Gook;Kim, Eun-Kyu;Kim, Young-Ho
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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    • pp.254-254
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    • 2011
  • The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

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Computing-Inexpensive Matrix Model for Estimating the Threshold Voltage Variation by Workfunction Variation in High-κ/Metal-gate MOSFETs

  • Lee, Gyo Sub;Shin, Changhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권1호
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    • pp.96-99
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    • 2014
  • In high-${\kappa}$/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage ($V_{TH}$) variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~$10^6$); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced $V_{TH}$ variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced $V_{TH}$ variation. The suggested model has been verified by experimental data, and the amount of WFV-induced $V_{TH}$ variation, as well as the $V_{TH}$ lowering is revealed.

비정질 및 단결정 실리콘에서 10~50 keV 에너지로 주입된 안티몬 이온의 분포와 열적인 거동에 따른 연구 (A Study on Implanted and Annealed Antimony Profiles in Amorphous and Single Crystalline Silicon Using 10~50 keV Energy Bombardment)

  • 정원채
    • 한국전기전자재료학회논문지
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    • 제28권11호
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    • pp.683-689
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    • 2015
  • For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

A Study on Temperature Dependent Super-junction Power TMOSFET

  • Lho, Young Hwan
    • 전기전자학회논문지
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    • 제20권2호
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    • pp.163-166
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    • 2016
  • It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

MOS구조에서의 원자층 증착 방법에 의한 $Ta_2O_{5}$ 박막의 전기적 특성에 관한 연구 (A Study on the Electrical Properties of $Ta_2O_{5}$ Thin Films by Atomic Layer Deposition Method in MOS Structure)

  • 이형석;장진민;임장권;하만효;김양수;송정면;문병무
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권4호
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    • pp.159-163
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    • 2003
  • ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.