• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.1-5
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• 2011

The epitaxial GaN layer of $120{\mu}m$ ~ $300{\mu}m$ thickness with a stripe Ti mask pattern is performed by hydride vapor phase epitaxy(HVPE). Ti strpie mask pattern is deposited by DC magnetron sputter on GaN epitaxial layer of $3{\mu}m$ thickness is grown by hydride vapor phase epitaxy(HVPE). Void are observed at point of Ti mask pattern when GaN layer is investigated by scanning electron microscope. The Crack of GaN layer is observed according to void when it is grown more thick GaN layer. The full width at half maximum of peak which is measured by X-ray diffraction is about 188 arcsec. It is not affected its crystallization by Ti meterial when GaN layer is overgrown on Ti stripe mask pattern according as it is measure FWHM of overgrowth GaN using Ti material against FWHM of first growth GaN epitaxial layer.

• Laser Solutions
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• v.15 no.4
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• pp.16-19
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• 2012

Due to the fact that the dimensions of circuit lines of IC substrates have been forecast to reduce rapidly, engraving the circuit line patterns with laser has emerged as a promising alternative. To engrave circuit line patterns in an IC substrate, we used a projection ablation technique in which a metal (INVAR) mask and a DPSS UV laser instead of an excimer laser are used. Results showed that the circuit line patterns engraved in the IC substrate have a width of about 15um and a depth of $13{\mu}m$. This indicates that the projection ablation with a metal mask and a DPSS UV laser could feasibly replace the semi-additive process (SAP).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.121-124
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• 2004

We have grown GaN layers with in-situ SiN mask by metal organic chemical vapor deposition(MOCVD) and study the physical properties of the GaN layer. We have also investigate the effect of the SiN mask on its optical property. By inserting a SiN mask, (102) the full width at half maximum(FWHM) decreased from 480 arcsec to 409 arcsec. The PL intensity of GaN with SiN mask improved 2 times to that without SiN mask. We have thus shown that the SiN mask improved significantly the physical and optical properties of the GgN layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.925-931
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• 2007

We successively fabricated the Ni metal mask by additive method and evaluated the effects of wetting agents addition on the microstructure, hardness, and friction coefficient. In the process, the additive patterns with fine hole and pitch were made by photolithography technique and subsequently Ni plate was electroformed on the patterns. We found that the microstructure and mechanical properties were significantly varied when the different combinations of the wetting agents were used. When the wetting agents of both SF-1 and SF-2 were added, the microstructure consisted of crystal and amorphous phases, the grain size reduced to 5-40 nm, the RMS value decreased to 11.4 nm and the wear resistance improved. In addition, the hardness was as high as 638 Hv which is higher than that of commercial stainless steel mask and this improvement is probably due to the presence of amorphous Phase and fine grain size. The improvement of the wear resistance can provide a higher reliability and a longer service life.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.345-346
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• 2009

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.97-100
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• 2004

We have grown GaN layers with in-situ SiN mask by metal organic chemical vapor deposition (MOCVD) and study the characteristic of the GaN layer. We have changed the deposition time of SiN mask from 45s to 5min and obtain th optimum condition in 45s. The PL intensity of GaN with SiN mask improved 2 times to that without SiN mask and the carrier concentraion increased from $3.5{\times}10^{16}cm^{-3}$ to $1.8{\times}10^{17}cm^{-3}$. We have thus shown that the SiN mask improved significantly the optical properties of the GaN layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.18-21
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher due to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method is applied with the rule based optical proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design nile is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.209-212
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher doc to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method Is applied with the rule based optical\ulcorner proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design rule is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.