• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.538-543
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• 1999

The theory of the reflow applied to metallization process was studied, and the factors affecting the reflow and the relation between the reflow and the grain growth were investigated. The driving force for the metal reflow is the difference in chemical potentials along the metal surface, and it causes the atom movement. On condition that metal interconnect is fabricated for semiconductor devices, surface diffusion is the primary atom movement mechanism. The metal reflow is influenced by reflow temperature, reflow time, reflow ambient, thin film thickness, thin film material, underlayer material, pattern size, and aspect ratio. It is supposed that the reflow characteristic varies according to the grain growth during the reflow, so the effect of the grain growth on the reflow should be considered.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1724-1729
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• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature/humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the Electrochemical migration

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.135-140
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• 2005

Although it was recently observed that severe fatigue damage was formed in Al or Cu interconnects due to the cyclic temperatures generated by Joule heating of the metal lines by the passage of alternating currents (AC), AC loading frequency effect on the damage evolution characteristics are not known so far. This work focused on the effect of AC loading frequency (100 Hz vs. 10 kHz) on the thermo-mechanical fatigue characteristics by using polycrystalline sputtered Cu lines with temperature cycles with amplitudes from 100 to $300^{\circ}C$. It was consistently observed that higher loading frequency accelerated damaged grain growth and led to earlier failure irrespective of Cu grain sizes. The frequency effect is believed to result from differences in the concentration of defects created by the deformation-induced motion of dislocations to the grain boundaries.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.370-370
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• 2012

Feature size of Cu interconnects keep shrinking into several tens of nanometer level. For this reason, the Cu interconnects face challenging issues such as increase of electro-migration, line-width dependent electrical resistivity increase, and gap-filling difficulty in high aspect ratio structures. As the thickness of the Cu film decreases below 30 nm, the electrical resistivity is not any more constant, but rather exponential. Research on alloying with other elements have been started to inhibit such escalation in the electrical resistivity. A faint trace of Al added in Cu film by sputtering was reported to contribute to suppression of the increase of the electrical resistivity. From an industrial point of view, we introduced cyclic metal organic chemical vapor deposition (MOCVD) in order to control Al concentration in the Cu film more easily by controlling the delivery time ratio of Cu and Al precursors. The amount of alloying element could be lowered at level of below 1 at%. Process of the alloy formation was applied into gap-filling to evaluate the performance of the gap-filling. Voidless gap-filling even into high aspect ratio trenches was achieved. In-depth analysis will be discussed in detail.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.57-67
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• 2002

Increased signal speed can be obtained in three ways: changing the layout and/or the ratio of the width to thickness of the metal lines, decreasing the specific resistance of the interconnect metal, and decreasing the dielectric constant of the insulating material (intermetal dielectric). Further advancement cannot be expected from changing layout or decreasing specific resistance. The only alternative is to use an insulating material with a lower dielectric constant than other ones used presently. A large variety of polymers has been proposed for use as materials with low dielectric constants for applications in microelectronics. In this review, the properties of selected polymers as well as various fabrication methods for polymer thin films are discussed. Based on the properties described so far, and the requirements for applications as intermetal dielectric material, the possibilities for further developments also are discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.571-572
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• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.