• 대한전자공학회논문지SD
• /
• 제39권9호
• /
• pp.19-27
• /
• 2002

실리콘 기판가 교차하는 금속 선의 밑층 기하구조를 고려한 연결선로의 특성이 정교하게 고안된 패턴을 가지고 실험적으로 분석되었다. 이 작업에서, 여러 종류의 밑층 기하구조에 따른 전송선로을 위한 테스트 패턴들을 고안하였고, 신호 특성과 반응은 S-parameter 와 TDR을 통해 측정되었다. 사용된 패턴은 두 개의 알루미늄 선과 한 개의 텅스텐 선을 가지는 deep-submicron CMOS DRAM 기술을 가지고 설계되고 제작되었다. 패턴위에서 측정되 결과 분석으로부터, 라인 파라메터들 (특히 라인 커패시턴스와 저항) 과 그것들에 의한 신호 왜곡에 대한 밑층 구조에 의한 효과는 무시 할수 없음을 발견하였다. 그러한 결과는 고속 클럭과 데이터 라인 같은 글로벌 신호 선이나 패키지 리드의 스큐 발렌스의 심도있고 유용한 이해에 도움이 된다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권6호
• /
• pp.854-859
• /
• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• Journal of Electrical Engineering and information Science
• /
• 제2권5호
• /
• pp.17-26
• /
• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• 한국재료학회지
• /
• 제9권5호
• /
• pp.538-543
• /
• 1999

금속 배선 공정에서 응용되고 있는 reflow에 관한 이론올 살펴보고, 금속 박막 reflow에 영향을 미치는 인자 및 re­flow와 grain growth의 관계를 고찰하였다. 금속 박막 reflow의 구동력은 표연 위치에 따른 chemical potential의 차이이며, 이러 한 구동력에 의하여 원자가 이동하게 된다. 반도체 소자의 금속 배선을 제작하는 조건에서 원자의 이동은 주로 surface diffusion에 의하여 이루어진다. 금속 박막의 reflow에 영향율 미치는 인자로는 reflow 온도, reflow 시간, reflow 분위기, 박막 두께, 박막 재료, underlayer 재료, 패턴 size, aspect ratio가 있으며, 박막을 reflow시키는 동안에 발생하는 grain growth에 의하여 reflow 특성이 변할 것으로 예상되므로 reflow 시 grain growth의 영향을 고려하여야 하리라 생각된다.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2007년도 춘계학술대회A
• /
• pp.1724-1729
• /
• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature/humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the Electrochemical migration

• 마이크로전자및패키징학회지
• /
• 제12권2호
• /
• pp.135-140
• /
• 2005

Although it was recently observed that severe fatigue damage was formed in Al or Cu interconnects due to the cyclic temperatures generated by Joule heating of the metal lines by the passage of alternating currents (AC), AC loading frequency effect on the damage evolution characteristics are not known so far. This work focused on the effect of AC loading frequency (100 Hz vs. 10 kHz) on the thermo-mechanical fatigue characteristics by using polycrystalline sputtered Cu lines with temperature cycles with amplitudes from 100 to $300^{\circ}C$. It was consistently observed that higher loading frequency accelerated damaged grain growth and led to earlier failure irrespective of Cu grain sizes. The frequency effect is believed to result from differences in the concentration of defects created by the deformation-induced motion of dislocations to the grain boundaries.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
• /
• pp.122-126
• /
• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.370-370
• /
• 2012

Feature size of Cu interconnects keep shrinking into several tens of nanometer level. For this reason, the Cu interconnects face challenging issues such as increase of electro-migration, line-width dependent electrical resistivity increase, and gap-filling difficulty in high aspect ratio structures. As the thickness of the Cu film decreases below 30 nm, the electrical resistivity is not any more constant, but rather exponential. Research on alloying with other elements have been started to inhibit such escalation in the electrical resistivity. A faint trace of Al added in Cu film by sputtering was reported to contribute to suppression of the increase of the electrical resistivity. From an industrial point of view, we introduced cyclic metal organic chemical vapor deposition (MOCVD) in order to control Al concentration in the Cu film more easily by controlling the delivery time ratio of Cu and Al precursors. The amount of alloying element could be lowered at level of below 1 at%. Process of the alloy formation was applied into gap-filling to evaluate the performance of the gap-filling. Voidless gap-filling even into high aspect ratio trenches was achieved. In-depth analysis will be discussed in detail.

• 마이크로전자및패키징학회지
• /
• 제9권3호
• /
• pp.57-67
• /
• 2002

반도체 칩의 신호처리속도를 향상시키기 위한 방법에는 세 가지가 있다. 첫 번째 방법은 금속배선의 배치(layout)를 바꾸는 것이고, 두 번째 방법은 배선으로 사용되는 금속의 비저항을 감소시키는 것이며, 세 번째 방법은 절연재료(insulating material)의 유전상수(dielectric constant)를 감소시키는 것이다. 첫 번째나 두 번째의 방법에 대해서는 많은 연구가 이루어졌고, 지금도 연구가 이루어지고 있다. 그러나 첫 번째나 두 번째의 방법을 통하여 얻을 수 있는 신호처리속도의 향상보다는 세 번째 방법을 통하여 얻을 수 있는 신호처리속도의 향상이 더 크다. 본 논문에서는 먼저 마이크로전자에 응용되기 위한 절연재료의 요구조건을 살펴보고, 지금까지 개발된 저유전율 고분자재료들을 간략하게 소개할 예정이다. 아울러 유전상수를 낮추기 위하여 최근 개발된 기공을 갖는 고분자재료들과 이들을 제조하기 위한 공정에 대해서도 간략하게 소개할 예정이다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.571-572
• /
• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.