• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.1
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• pp.35-40
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• 2017

A most important progress in civilization was the introduction of mass production. One of main methods for mass production is die-casting molds. Due to the high velocity of the liquid metal, aluminum die-casting is so complex where flow momentum is critical matter in the mold filling process. Actually in complex parts, it is almost impossible to calculate the exact mold filling performance with using experimental knowledge. To manufacture the lightweight automobile bodies, aluminum die-castings play a definitive role in the automotive part industry. Due to this condition in the design procedure, the simulation is becoming more important. Simulation can make a casting system optimal and also elevate the casting quality with less experiment. The most advantage of using simulation programs is the time and cost saving of the casting layout design. For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_BR2E, Computer Aided Engineering (CAE) simulation was performed with three layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with three models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflows. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.105-105
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• 2012

We have developed a photoemission-assisted plasma-enhanced chemical vapor deposition (PAPE-CVD) [1,2], in which photoelectrons emitting from the substrate surface irradiated with UV light ($h{\nu}$=7.2 eV) from a Xe excimer lamp are utilized as a trigger for generating DC discharge plasma as depicted in Fig. 1. As a result, photoemission-assisted plasma can appear just above the substrate surface with a limited interval between the substrate and the electrode (~10 mm), enabling us to suppress effectively the unintended deposition of soot on the chamber walls, to increase the deposition rate, and to decrease drastically the electric power consumption. In case of the deposition of DLC gate insulator films for the top-gate graphene channel FET, plasma discharge power is reduced down to as low as 0.01W, giving rise to decrease significantly the plasma-induced damage on the graphene channel [3]. In addition, DLC thickness can be precisely controlled in an atomic scale and dielectric constant is also changed from low ${\kappa}$ for the passivation layer to high ${\kappa}$ for the gate insulator. On the other hand, negative electron affinity (NEA) of a hydrogen-terminated diamond surface is attractive and of practical importance for PAPECVD, because the diamond surface under PAPE-CVD with H2-diluted (about 1%) CH4 gas is exposed to a lot of hydrogen radicals and therefore can perform as a high-efficiency electron emitter due to NEA. In fact, we observed a large change of discharge current between with and without hydrogen termination. It is noted that photoelectrons are emitted from the SiO2 (350 nm)/Si interface with 7.2-eV UV light, making it possible to grow few-layer graphene on the thick SiO2 surface with no transition layer of amorphous carbon by means of PAPE-CVD without any metal catalyst.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1572-1575
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• 2005

Poly(vinyl phenol)(PVP)/$TiO_2$ nanocomposite the films have been prepared incorporating metal alkoxide with vinyl polymer to obtain high dielectric constant gate insulating material for a organic thin film transistor. The surface composition, the morphology, and the thermal and electrical properties of the hybrid nanocomposite films were observed by ESCA, scanning electron microscopy (SEM), atomic force microscopy(AFM), and thermogravimetric analysis (TGA). Thin hybrid films exhibit much higher dielectric constants (7.79 at 40wt% metal alkoxide).

• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• Journal of IKEEE
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• v.22 no.1
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• pp.180-184
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• 2018

Gallium oxide ($Ga_2O_3$) and silicon carbide (SiC) are the material with the wide band gap ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV). These electronic properties allow high blocking voltage. In this work, we investigated the characteristic of $Ga_2O_3$ and 4H-SiC vertical depletion-mode metal-oxide-semiconductor field-effect transistors. We demonstrated that the blocking voltage and on-resistance of vertical DMOSFET is dependent with structure. The structure of $Ga_2O_3$ and 4H-SiC vertical DMOSFET was designed by using a 2-dimensional device simulation (ATLAS, Silvaco Inc.). As a result, 4H-SiC and $Ga_2O_3$ vertical DMOSFET have similar blocking voltage ($Ga_2O_3-1380V$, SiC-1420 V) and then when gate voltage is low, $Ga_2O_3-DMOSFET$ has lower on-resistance than 4H-SiC-DMOSFET, however, when gate voltage is high, 4H-SiC-DMOSFET has lower on-resistance than $Ga_2O_3-DMOSFET$. Therefore, we concluded that the material of power device should be considered by the gate voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.10
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• pp.3917-3922
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• 2010

In this paper, 3 stage amplifier MMIC was designed and fabricated with U-band optimized epitaxal pHEMT that produced by large signal characterization and modeling for 60 GHz band. The pHEMT used in this paper, the gate $0.12\;{\mu}m$ length and total gate width of $100\;{\mu}m$, $200\;{\mu}m$ has been modeled using the large signal designed with negative feedback and MCLF instead of MIM capacitor for improving stability. Fabricated MMIC $2.5{\times}1.5mm^2$ size, current about 40 mA, operating frequency 59.5~60.5 GHz, gain 19.9~18.6 dB, input matching characteristics -14.6~-14.7 dB, output matching characteristics -11.9~-16.3 dB and output -5 dBm characteristics were obtained.