• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.11
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.9
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• pp.671-676
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• 2012

In this paper, TCAD assessment of 30-V class n-channel EDMOS (extended drain metal-oxide-semiconductor) transistors with DWFG (dual work function gate) structure are described. Gate of the DWFG EDMOS transistor is composed of both p- and n-type doped region on source and drain side. Additionally, lengths of p- and n-type doped gate region are varied while keeping physical channel length. Two-dimensional device structures are generated trough TSUPREM-4 and their electrical characteristics are investigated with MEDICI. The DWFG EDMOS transistor shows improved electrical characteristics than conventional device - i.e. higher transconductance ($g_m$), better drain output current ($I_{ON}$), reduced specific on-resistances ($R_{ON}$) and higher breakdown characteristics ($BV_{DSS}$).

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.2
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• ETRI Journal
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• v.38 no.4
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• pp.645-653
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• 2016

This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.