• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.522-529
• /
• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2003.06a
• /
• pp.168-169
• /
• 2003

최근 세계적 주목을 받고 있는 spin FET 소자는 반도체에 주입된 spin 편향된 전자가 gate voltage(V$_{G}$)에 의해 반도체 계면에 유도된 전기장의 영향을 받아, Spin 세차운동을 하는 mechanism(Rashba 효과)이 근간을 이루고 있다. 작은 band gap을 가지는 반도체(narrow gap 반도체)는 작은 유효질량의 전자에 의해서 이러한 Rashba 효과를 크게 할 수 있어서, spin FET 구현을 위한 강력한 후보이며, 요즘 한창 연구되고 있는 주제이기도 하다. Rashba 효과가 저자기장 영역에서의 weak antilocalization효과로 나타남을 이용하여, 본 논문에서는 metal gate가 형성된 HgCdTe FET를 제작하여(FET1 시료, Fig. 1(a)참조), V$_{G}$에 따른 weak localization(WL) 및 weak antilocalization(WAL) 효과를 얻었다. 또한, Rashba 효과에 의한 spin 세차운동을 측정할 수 있는 소자(FET3 시료, Fig.1(b) 참조)를 제작하여 spin FET 구조에 대하여 연구하였다.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.3
• /
• pp.1169-1173
• /
• 2015

This paper presents vertical carbon nanotube (CNT) field effect transistors (FETs). For the first time, the author successfully fabricated vertical CNT-based FETs on an anodized aluminum oxide (AAO) template by using atomic layer deposition (ALD). Single walled CNTs were vertically grown and aligned with the vertical pores of an AAO template. By using ALD, a gate oxide material (Al₂O₃) and a gate metal (Au) were centrally located inside each pore, allowing the vertical CNTs grown in the pores to be individually gated. Characterizations of the gated/vertical CNTs were carried and the successful gate integration with the CNTs was confirmed.

• 한국컴퓨터산업교육학회:학술대회논문집
• /
• 2003.11a
• /
• pp.67-70
• /
• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• Journal of Drive and Control
• /
• v.12 no.4
• /
• pp.15-20
• /
• 2015

Unlike a typical metal spring, a gas spring uses compressed gas contained in a cylinder and compressed by a piston to exert a force. A common application includes automobiles where gas spring are incorporated into the design of open struts that support the weight of tail gate. They are also used in furniture such as office chairs, and in medical and aerospace applications. The gas spring works by the application of pressurized gas (nitrogen) contained in a cylinder. The internal pressure of the gas spring greatly exceeds atmospheric pressure. This differential in pressure exists at any rod position and generates an outward force on the rod, making the gas spring extend. In this paper, we investigated the dynamic characteristics of a gas spring on an automotive tail gate system.

• Journal of the Korean Vacuum Society
• /
• v.11 no.2
• /
• pp.103-107
• /
• 2002

Metal/ferroelectric/semiconductor field effect transistors(MFSFET′s) with various gate electrodes, that are aluminum, platinum and poly-Si, using rapid thermal annealed $LiNbO_3$/Si(100) structures were fabricated and the properties of the FET′s have been discussed. The drain current of the "on" state of FET with Pt electrode was more than 3 orders of magnitude larger than the "off" state current at the same "read" gate voltage of 1.5 V, which means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about $10^3$ s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.219-220
• /
• 2000

We propose a new method for the formation of an aluminum parting layer in the fabrication of field emitter arrays, in which we used a reflow property of aluminum at a lower temperature than the deformation point of glass. After the sputtered aluminum layer on the gate metal was etched for the formation of gate holes, we carried out a rapid thermal annealing process, by which the aluminum slightly diffused into the gate hole. This reflowed aluminum could be used as a parting layer and emitter arrays were easily fabricated using this method.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.342-342
• /
• 2011

산화막은 반도체 공정 중 가장 핵심적이며 기본적인 물질이다. 반도체 소자에서 내부의 캐리어들의 이동을 막고 전기를 절연시켜주는 절연체로서 역할을 하게 된다. 실제로 제작된 산화막에서는 dangling bond 혹은 내부에 축적되는 charge들의 의해 leakage가 생기게 되고 그에 따라 산화막의 특성은 저하되게 된다. 내부에서 특성을 저하시키는 defect을 감소시키기 위해 Plasma Treatment에 따른 특성변화를 관찰하였다. 본 연구에서는 최적화 시킨 Flexible TFT제작을 위해 저온에서 Silicon Oxide로 형성한 Gate Insulator에 각각 N2O, H2, NH3가스를 주입 후 Plasma처리를 하였다. 특성화 시킨 Gate Insulator를 이용하여 MIS(Metal-Insulator-Semiconductor)구조를 제작 후 C-V curve특성변화, Dit의 감소, Stress bias에 따른 stability를 확인 하였다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.148-150
• /
• 2009

We have developed 15 inch, 130 blocks local dimming FEL using printed CNT emitters, in which multiple FE blocks were built with a common gate electrode. Cathode electrode formed by the double-metal technique, in which an insulator is interposed between the addressing bus and cathode electrode.

• ETRI Journal
• /
• v.32 no.4
• /
• pp.530-539
• /
• 2010

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.