• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.57-57
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• 2009

반도체 device가 고집적화 및 다층화 되어짐에 따라 현재 사용되고 있는 구리 interconnect의 확산방지막인 Ta/TaN은 많은 문제가 발생하고 있다. 고집적화 된 반도체 소자에 적용시키기에는 Ta/TaN 확산 방지막의 고유 저항값이 매우 크고, 구리의 증착에 필요한 seed layer의 크기도 문제화 된다고 보고되어지고 있다. 이러한 이유로 인해 점차 고집적화 되어지는 반도체 기술에 맞추어 새로운 확산 방지막에 대한 연구가 현재 활발히 이루어지고 있다. 이에 새로운 확산 방지막으로써 대두되고 연구되고 있는 재료가 Ruthenium (Ru)이다. Ru은 공기 중에서 매우 안정하고 고유저항 값 또한 $13\;{\mu}{\Omega}\;cm$의 Ta에 비해 $7.1\;{\mu}{\Omega}\;cm$의 매우 작은 고유저항 특성을 가지고 있다. 또한, Ru은 구리와의 우수한 접착성으로 인해 구리의 interconnect의 형성에 있어 seed layer가 필요하지 않을 뿐만 아니라 높은 annealing 온도에서도 무시할 만큼 작은 solid solubility를 가지며 구리와의 계면에서 새로운 화합물을 형성하지 않으며 annealing시 구리의 delamination을 유발시키지도 않는다. 이에 따라, 평탄화와 소자 분리를 위하여 chemical mechanical planarization (CMP) 공정이 필요하게 되었다. 하지만, Ru의 noble한 성질과 Ru 확산방지막 CMP공정 시 노출되는 다른 이종 물질 사이의 최적화 된 selectivity를 구현하는데 많은 어려움이 있다. 이로인해 Ru 확산 방지막을 위한 CMP slurry에 대한 연구는 아직 미흡한 수준이다. 본 연구에서는 Ru이 확산방지막으로 사용되었을 때 이를 위한 CMP slurry에 대한 평가와 연구가 이루어졌다. Slurry 조성과 농도 및 pH에 따른 전기 화학적 분석을 통하여 slurry 내에서 각각의 막질들이 어떠한 상태로 존재하는지 분석해 보았다. 또한, Ru을 비롯한 이종막질들의 etch rate, removal rate와 selectivity에 대한 연구가 진행되었다. 최종적으로 Ru 확산방지막 CMP를 위한 최적화된 slurry를 제안하였다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.30-34
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• 2023

Since dishing in the CMP process is a major factor that hinders the uniformity of the semiconductor thin film, many studies have focused this issue to improve the non-uniformity of the film due to dishing. In the metal layer, the dishing mainly occurs in the central part of the metal due to a difference in a selection ratio between the metal and the dielectric, thereby generating a step on the surface of the metal layer. Factors that cause dishing include the shape of the thin film, the chemical reaction of the slurry, thermal deformation, and the rotational speed of the pad and head, and dishing occurs due to complex interactions between them. This study analyzed the stress generated on the metal layer surface in the CMP process using ANSYS software, a commercial structure analysis program. The stress caused by the vertical load applied from the pad was analyzed by changing the area density and line width of the dummy metal. As a result of the analysis, the stress in the active region decreased as the pattern density and line width of the dummy metal increased, and it was verified that it was valid compared with the previous study that studied the dishing according to the dummy pattern density and line width of the metal layer. In conclusion, it was confirmed that there is a relationship between dishing and normal stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.889-893
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• 2006

Chemical mechanical polishing (CMP) achieves surface planrity through combined mechanical and chemical means. The role of slurry is very important in metal CMP. Slurry used in metal CMP normally consists of oxidizers, complexing agents, corrosion inhibitors and abrasives. This paper investigates the effects of citric acid as a complexing agent for Cu CMP with $H_2O_2$. In order to study chemical effects of citric acid, X-ray photoelectron spectroscopy (XPS) was peformed on Cu sample after etching test. XPS results reveal that CuO, $Cu(OH)_2$ layer decrease but $CU/CU_2O$ layer increase on Cu sample surface. To investigate nanomechanical properties of Cu sample surface, nanoindentation was performed on Cu sample. Results of nanoindentation indicate wear resistance of Cu surface decrease. According to decrease of wear resistance on Cu surface removal rate increases from $285\;{\AA}/min\;to\;8645\;{\AA}/min$ in Cu CMP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.515-520
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• 2005

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. Also CMP process got into key process for global planarization in the chip manufacturing process. In this study, potentiodynamic polarization was carried out to investigate the influences of $H_2O_2$ concentration and metal oxide formation through the passivation on tungsten and titanium. Fortunately, the electrochemical behaviors of tungsten and titanium are similar, an one may expect. As an experimental result, electrochemical corrosion of the $5\;vol\%\;H_2O_2$ concentration of tungsten and titanium films was higher than the other concentrations. According to the analysis, the oxidation state and microstructure of surface layer were strongly influenced by different oxidizer concentration. Moreover, the oxidation kinetics and resulting chemical state of oxide layer played critical roles in determining the overall CMP performance. Therefore, we conclude that the CMP characteristics tungsten and titanium metal layer including surface roughness were strongly dependent on the amounts of hydrogen peroxide oxidizer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.378-383
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• 2004

Tungsten is widely used as a plug for the multi-level interconnection structures. However, due to the poor adhesive properties of tungsten(W) on SiO$_2$ layer, the Ti/TiN barrier layer is usually deposited onto SiO$_2$ for increasing adhesion ability with W film. Generally, for the W-CMP(chemical mechanical polishing) process, the passivation layer on the tungsten surface during CMP plays an important role. In this paper, the effect of oxidant on the polishing selectivity of W/Ti/TiN layer was investigated. The alumina(A1$_2$O$_3$)-based slurry with $H_2O$$_2$ as the oxidizer was used for CMP applications. As an experimental result, for the case of 5 wt％ oxidizer added, the removal rates were improved and polishing selectivity of 1.4:1 was obtained. It was also found that the CMP characteristics of W and Ti metal layer including surface roughness were strongly dependent on the amounts of $H_2O$$_2$ oxidizer.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.529-529
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• 2007

Ruthenium (Ru) is a white metal and belongs to platinum group which is very stable chemically and has a high work function. It has been widely studied to apply Ru as an electrode material in memory devices and a Cu diffusion barrier metal for Cu interconnection due to good electrical conductivity and adhesion property to Cu layer. To planarize deposited Ru layer, chemical mechanical planarization(CMP) was suggested. However, abrasive particle can induce particle contamination on the Ru layer surface during CMP process. In this study, zeta potentials of Ru and interaction force of alumina particles with Ru substrate were measured as a function of pH. The etch rate and oxidation behavior were measured as a function of chemical concentration of several organic acids and other acidic and alkaline chemicals. PRE (particle removal efficiency) was also evaluated in cleaning chemical.