• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.1
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• pp.87-96
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• 2006

In this paper, we examine general digital evidence collection process which is according to RFC3227 document[l], and establish specific steps for memory information collection. Besides, we include memory dump process to existing digital evidence collection process, and examine privacy information through dumping real user's memory and collecting pagefile which is part of virtual memory system. Especially, we discovered sensitive data which is like password and userID that exist in the half of pagefiles. Moreover, we suggest each analysis technique and computer forensic process for memory information and virtual memory.

• Journal of Information Processing Systems
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• v.2 no.2
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• pp.76-81
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• 2006

A PDA is used mainly for downloading data from a stationary server such as a desktop PC in an infrastructure network based on wireless LAN. Thus, the overall performance depends heavily on the performance of such downloading with PDA. Unfortunately, for a PDA the time taken to receive data from a PC is longer than the time taken to send it by 53%. Thus, we measured and analyzed all possible factors that could cause the receiving time of a PDA to be delayed with a test bed system. There are crucial factors: the TCP window size, file access time of a PDA, and the inter-packet delay that affects the receiving time of a PDA. The window size of a PDA during the downstream is reduced dramatically to 686 bytes from 32,581 bytes. In addition, because flash memory is embedded into a PDA, writing data into the flash memory takes twice as long as reading the data from it. To alleviate these, we propose three distinct remedies: First, in order to keep the window size at a sender constant, both the size of a socket send buffer for a desktop PC and the size of a socket receive buffer for a PDA should be increased. Second, to shorten its internal file access time, the size of an application buffer implemented in an application should be doubled. Finally, the inter-packet delay of a PDA and a desktop PC at the application layer should be adjusted asymmetrically to lower the traffic bottleneck between these heterogeneous terminals.

• Korean Journal of Metals and Materials
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• v.48 no.3
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.56-56
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• 2009

In this study, we fabricated the engineered $SiO_2/Si_3N_4/SiO_2$(ONO) tunnel barrier with high-k $HfO_2$ trapping layer for application high performance flash MLC(Multi Level Cell). As a result, memory device show low operation voltage and stable memory characteristics with large memory window. Therefore, the engineered tunnel barrier with ONO stacks were useful structure would be effective method for high-integrated MLC memory applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.48-51
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• 1991

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.33-36
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• 1994

The characteristics of the nonvolatile MONOS memory devices as the nitride thickness is scaled down while maintaining constant tunneling oxide thickness and blocking oxide thickness have been investigated in order to obtain the 5V-programmable E$^2$PROM. We have found that 1V memory window for a 5V programming voltage and 10 year data retention can be achieved in the scaled MONOS memory devices with a 50 blocking oxide, a 57 nitride and a 19 tunneling oxide.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1218-1226
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• 1999

In decoding the turbo codes, the sliding window BCJR algorthm, derived from the BCJR algorithm, permits a continuous decoding of the coded sequence without requiring trellis fermination of the constituent codes and uses reduced memory span. However, the number of computation required is greater than that of BCJR algorithm and no study on the effect of the window length has been reported. In this paper, we propose an eddicient sliding window type scheme which maintains the advantages of the conventional sliding window algorithm, reduces its computational burdens, and improves is BER performance. A guideline is first presented to determine the proper window length and then a computationally efficient sliding window BCJR algorithm is obtained by allowing the window to be forwarded in multi-step. Simulation results show that the proposed scheme outperforms the conventional sliding window BCJR algorithm with reduced complexity. It gains 0.1dB SNR improvements over the conventional method for the constraint length 3 and BER $10^{-4}$

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.301-305
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• 2009

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.464-469
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• 2002

$SrBi_2Nb_2O_9(SBN)$ thin films were grown on Pt/Ti/Si and p-type Si(100) substrates by rf-magnetron co-sputtering method using two ceramic targets, $SrNb_2O_6\; and \;Bi_2O_3$. The structural and electrical characteristics have been investigated to confirm the possibility of the SBN thin films for the applications to destructive and nondestructive read out ferroelectric random access memory(FRAM). For the optimum growth condition X-ray diffraction patterns showed that SBN films had well crystallized Bi-layered perovskite structure after $700^{\circ}C$ heat-treatment in furnace. From this specimen we got remnant polarization $(2P_r)$ of about 6 uC/$\textrm{cm}^2$ and coercive voltage $(V_c)$ of about 1.5 V at an applied voltage of 5 V. The leakage current density was $7.6{\times}10^{-7}$/A/$\textrm{cm}^2$ at an applied voltage of 5V. And for the NDRO-FRAM application, properties of SBN films on Si substrate has been investigated. From transmission electron microscopy (TEM) analysis, we found the furnace treated sample had a native oxide about 2 times thicker than the RTA treated sample and this thick native oxide layer had a bad effect on C-V characteristics of SBN/Si thin film. After $650^{\circ}C$ RTA process, we got the improved memory window of 1.3 V at an applied voltage of 5 V.