• Journal of Korea Multimedia Society
• /
• v.10 no.11
• /
• pp.1516-1522
• /
• 2007

We had proposed the FPA(Fixed Partition Averaging) method in order to improve the storage requirement and classification rate of the Memory Based Reasoning. The algorithm worked not bad in many area, but it lead to some overhead for memory usage and lengthy computation in the multi classes area. We propose an Repetitive FPA algorithm which repetitively partitioning pattern space in the multi classes area. Our proposed methods have been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.6
• /
• pp.49-55
• /
• 2012

A study on e-book viewer terminal in the native language of the platform-dependent studies are based, This is inefficient in memory usage and screen rendering speed, and there are frequent system updates, e-book viewer, the nature of mobile terminal platform application compatibility issues may occur. In this paper, using the mobile app framework in order to design e-book e-book viewer, analyzed the structure of ePub file parser and file more structured modules were designed and MVC. Designed and implemented to test the functionality of the memory information that is currently running to provide the ability to show the relationship of DDMS and layout components were used to show Hierarchy Viewer. As a result, rendering the screen 150%, 84% in the heap memory usage, improved performance was confirmed.

• Asia Marketing Journal
• /
• v.12 no.1
• /
• pp.31-50
• /
• 2010

People have competing desires. Hence, people not only chase others' choices due to the need for assimilation but also avoid others' choices due to the need for differentiation. This study attempts to uncover under which conditions consumers assimilate with or differentiate from others' choices. Specifically, the study extends previous research about the effect of others' choices by focusing on the effect of a choice situation (purchase vs. usage) based on the conformity theory and the uniqueness theory. It was found that purchase (vs. usage) situation makes people more conform to others in case of identity-irrelevant product (e.g., USB memory stick). Also, the effect of the choice situation was moderated by the perceived identity-relevance level in case of identity-relevant product (e.g., jeans).

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.7
• /
• pp.476-487
• /
• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.4
• /
• pp.368-380
• /
• 2005

File systems for flash memory that is widely used as a storage device for mobile devices should provide not only high-performance data reads and writes but also a guarantee on the data integrity even on a power failure. In this paper, we explain the design and implementation of a file system for flash memory that considers flash memory's physical characteristics and the data layout in the file system to give an optimized write performance. This file system guarantees the reliability against various system failures including a power failure by using the transaction concept in write processing. In addition, the file system minimizes the memory usage by using a simple static mapping. In the paper, we also describe the implementation of the file system and compare its performance with other existing flash memory ille systems.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.6
• /
• pp.99-107
• /
• 2020

In this paper, we analyze the characteristics of mobile cache, which is used to improve the data access speed when executing applications on mobile devices, and verify the importance of mobile cache through a cache data access experiment. The mobile device market has grown at a fast pace over the past decade; however, battery limitations and size, price considerations restrict the usage of fast hardware. Thus, their performance are supplemented by using a memory buffer structure such as the cache memory. The analysis mainly focuses on cache size, hierarchical structure of cache, cache replacement policy, and the effect these features has on mobile performance. For the experimental data, we applied a data set from a microprocessor system study, originally used to test the cache performance. In the experimental results, the average data access speed on a mobile device showed a performance improvement of up to 10 times with the presence of cache memory than without. Accordingly, the cache memory was helpful for the performance improvement of a mobile device when the specifications were identical.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.15 no.3
• /
• pp.837-852
• /
• 2021

Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.3
• /
• pp.147-160
• /
• 2010

The system virtualization shows interest in the consolidation of servers for the efficient utilization of system resources. There are many various researches to utilize a server machine more efficiently through the system virtualization technique, and improve performance of the virtualization software. These researches have studied with the activity to control the resource allocation of virtual machines dynamically focused on CPU, or to manage resources in the cross-machine using the migration. However, the researches of the memory management have been wholly lacking. In this respect, the use of memory is limited to allocate the memory statically to virtual machine in server consolidation. Unfortunately, the static allocation of the memory causes a great quantity of the idle memory and decreases the memory utilization. The underutilization of the memory makes other side effects such as the load of other system resources or the performance degradation of services in virtual machines. In this paper, we suggest the dynamic allocation of the memory in Xen to control the memory allocation of virtual machines for the utilization without the performance degradation. Using AR model for the prediction of the memory usage and ACO (Ant Colony Optimization) algorithm for optimizing the memory utilization, the system operates more virtual machines without the performance degradation of servers. Accordingly, we have obtained 1.4 times better utilization than the static allocation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.1-9
• /
• 2012

Quantum-Inspired Evolutionary Algorithm(QEA) contains sufficient data-level parallelism to be naturally accelerated on GPUs. For an efficient reduction of execution time, however, careful task-mapping should be done to properly reflect the characteristics of CPU and GPU. Furthermore, when deciding which part of the application should run on GPU, we need to consider the data transfer between CPU and GPU memory spaces as well as the data-level parallelism. In addition, the usage of zero-copy host memory, proper choice of the execution configuration, and thread organization considering memory coalescing is important to further reduce the execution time. With all these techniques, we could run QEA 3.69 times faster on average in comparison with the multi-threading CPU for the case of 0-1 knapsack problem with 30,000 items.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.40-47
• /
• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.