1 |
A. Gutierrez, R. G. Dreslinski, T. F. Wenisch, T. Mudge, A. Saidi, C. Emmons, and N. Paver, "Full-system analysis and character ization of interactive smartphone applications", IEEE International Symposium on Workload Characterization, In Proceedings of the 2011 IEEE International Symposium on Workload Characterization, No. 11, pp. 81-90, December 2011. 10.1109/IISWC.2011.6114205
|
2 |
T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee, J. Lee, K. Ha, Y. Choi, Y. Cho, Y. Bae, T. Jang, C. Park, K. Park, S. Jang, and J. Choi, "A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation", IEEE Journal of Solid-State Circuits, Vol. 50, No. 1, pp. 178-190, January 2015. 10.1109/JSSC.2014.2353799
DOI
|
3 |
H. Kim, M. Ryu, and U. Ramachandran, "What is a good buffer cache replacement scheme for mobile flash storage?", Association for Computing Machinery, In Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems, No. 12, pp. 235-246, June 2012. 10.1145/ 2254756.2254786
|
4 |
A. J. Smith, "Cache Memories", ACM Computing Surveys, Vol. 14, No. 3, pp. 473-530, September 1982. 10.1145/356887.356892
DOI
|
5 |
S. Jiang, and X. Zhang, "LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache perfor mance", Association for Computing Machinery, In Proceedings of the 2002 ACM SIGMETRICS international conference on Meas urement and modeling of computer systems, No. 2, pp. 31-42, June 2002. 10.1145/511334.511340
|
6 |
J. L. Baer, and W. H. Wang, "On the inclusion properties for multi-level cache hierarchies", Association for Computing Machinery, In 25 years of the international symposia on Computer architecture, No. 98, pp. 345-352, August 1998. 10.1145/285930.285994
|
7 |
S. Park, D. Jung, J. Kang, J. Kim, and J. Lee, "CFLRU: a replacement algorithm for flash memory", Association for Computing Machinery, In Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedde d systems, No. 8, pp. 234-241, October 2006. 10.1145/1176760.1176789
|
8 |
M. D. Lam, E. E. Rothberg, and M. E. Wolf, "The cache perfor mance and optimizations of blocked algorithms", Association for Computing Machinery, In Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, No. 5, pp. 63-74, April 1991. 10.1145/106972.106981
|
9 |
A. Asaduzzaman, I. Mahgoub, P. Sanigepalli, H. Kalva, R. Shankar, and B. Furht, "Cache optimization for mobile devices running multimedia applications", IEEE Sixth International Symposium on Multimedia Software Engineering, In Proceedings of the IEEE Sixth International Symposium on Multimedia Software Engineering, No. 4, pp. 499-506, December 2004. 10.1109/MMSE.2004.34
|
10 |
J. E. Smith, and J. R. Goodman, "Instruction Cache Replacement Policies and Organizations", IEEE Transactions on Computers, Vol. 34, No. 3, pp. 234-241, March 1985. 10.1109/TC.1985.1676566
|
11 |
H. Al-Zoubi, A. Milenkovic, and M. Milenkovic, "Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite", Association for Computing Machinery, In Proceedings of the 42nd annual Southeast regional conference, No. 42, pp. 267-272, April 2004. 10.1145/986537.986601
|
12 |
T. Johnson, and D. Shasha., "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm", Morgan Kaufmann Publishers Inc, In Proceedings of the 20th International Conference on Very Large Data Bases, No. 94, pp. 439-450, September 1994. 10.5555/645920.672996
|
13 |
S. Przybylski, M. Horowitz, and J. Hennessy, "Characteristics of performance-optimal multi-level cache hierarchies", Associatio n for Computing Machinery, In Proceedings of the 16th Annual International Symposium on Computer Architecture, No. 89, pp. 114-121, April 1989. 10.1145/74925.74939
|
14 |
WikiChip, https://en.wikichip.org/wiki/samsung/exynos/9825.
|
15 |
P. Panda, G. Patil, and B. Raveendran, "A survey on replacement strategies in cache memory for embedded systems", 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, pp. 12-17, August 2016. 10.1109/DISCOVER.2016.7806218
|
16 |
H. Moon, and S. Jee, "An Energy Efficient and High Performance Data Cache Structure Utilizing Tag History of Cache Addresses", The Kips Transactions: Part A, Vol. 14, No. 1, pp. 55-62, February 2007. 10.3745/KI PSTA.2007.14-A.1.055
|
17 |
Wikipedia, Apple A12X Processor, https://en.wikipedia.org.
|
18 |
Passmark, https://www.passmark.com.
|
19 |
Wicker, L2-Cache-Simulator, https://github.com/wicker/L2-Cache-Simulator.
|
20 |
Wikipedia, https://en.wikipedia.org/wiki/MESI_protocol.
|
21 |
Y. Kim, and Y. Song, "Impact of processor cache memory on storage performance", Institute of Electrical and Electronics Engineers Inc., In Proceedings of the International SoC Design Conference 2017, pp. 304-305, November 2017. 10.1109/ISOCC.2017.8368908
|
22 |
J. Ahmed, M. Y. Siyal, S. Najam, and Z. Najam, "Multiprocessors and Cache Memory", SpringerBriefs in Applied Sciences and Technology, Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System, November 2017. 10.1007/978-981-10-3120-5_1
|
23 |
H. Mehboob, and H. A. Niaz, "ENHANCE THE PERFORMANCE OF ASSOCIATIVE MEMORY BY USING NEW METHODS", VFAST Transactions on Software Engineering, Vol. 12, No. 3, pp. 49-56, December 2017.
|