• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.144-145
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• 2007

Phase change random access memory is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to develop the new phase change material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of phase change material parameters using finite element analysis.

• Transactions of the Society of Information Storage Systems
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• v.7 no.1
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• pp.42-46
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• 2011

Holographic Data Storage System (HDSS), one of the next generation data storage devices, is a 2-dimensional page oriented memory system using volume hologram. HDSS has many noise sources such as crosstalk, scattering and inter pixel interference, etc. The noise source is changing intensity of the light used for carrying the data signal in HDSS. The inter pixel interference results in decrease of Signal to Noise Ratio and increase of Bit Error Rate. In order to improve these problems, this paper proposes to compensate the inter pixel interference with simple interference mask.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.26 no.3
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• pp.67-73
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• 2003

Manufacturing technologies of compound semiconductor are similar to the process of memory device, but management technology of manufacturing process for compound semiconductor is not enough developed. Semiconductor manufacturing environment also has been emerged as mass customization and open foundry service so integrated manufacturing system is needed. In this study we design the integrated manufacturing system for compound semiconductor fabrication t hat has monitoring of process, reduction of lead-time, obedience of due-dates and so on. This study presents integrated manufacturing system having database system that based on web and data acquisition system. And we will implement them in the actual compound semiconductor fabrication.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.633-636
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• 2022

The reduction of energy consumption at the base station (BS) has become more important recently. In this paper, we consider the adaptive muting of the antennas based on the predicted future traffic load to reduce the energy consumption where the number of active antennas is adaptively adjusted according to the predicted future traffic load. Given that traffic load is sequential data, three different RNN structures, namely long-short term memory (LSTM), gated recurrent unit (GRU), and bidirectional LSTM (Bi-LSTM) are considered for the future traffic load prediction. Through the performance evaluation based on the actual traffic load collected from the Afghanistan telecom company, we confirm that the traffic load can be estimated accurately and the overall power consumption can also be reduced significantly using the antenna musing.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.1203-1206
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• 2021

소음은 난청, 스트레스 등의 원인이 된다. 본 연구에서는 ANC(Active Noise Cancellation)을 바탕으로, 기술적인 방법을 통해 소음을 저감 시키는 스피커를 구현하였다. ANC 란 소음 주파수의 위상을 180° 변환하여 주파수와 레벨이 동일한 역 소음을 발생시켜 주변 소음을 저감, 차단하는 기술이다. 현재 시중 제품들에 적용되는 일반적인 ANC 의 경우, 피드백(Feedback) 방식이라는 점과 시간 지연(Time gap)이 발생한다는 한계가 있다. 이를 보완하기 위해 AI 학습으로 소음을 미리 예측하여 시간 지연을 줄이는 방법을 고안했다. 순환 신경망(RNN)의 장기의존성 문제를 해결하는 시계열 예측 딥러닝 알고리즘인 LSTM(Long Short-Term Memory Network) 모델을 사용하였다. 또한, AI 학습 효율을 향상시킬 수 있는 하드웨어 장비들을 활용하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.1108-1109
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• 2023

본 논문은 선박 내부 소음을 효과적으로 감소시키기 위한 ANC(Active Noise Cancellation)및 인공 지능 (AI) 결합 시스템의 개발과 적용에 관한 연구를 다룬다. 선박 환경에서의 소음은 승원의 스트레스 증가와 불편을 초래하므로, 이를 해결하기 위한 방법을 제안하고자 한다. 외부 소음과 내부 소음 데이터를 수집하고, STFT(Short-Time Fourier Transform)알고리즘을 통해 소음 데이터를 분석 가능한 형태로 전처리한다. 그 후, LSTM(Long Short-Term Memory)알고리즘을 사용하여 선박 외부에서 발생한 소음을 입력으로 받아 내부에서 들리는 외부 소음을 예측하고 제어하는 모델을 훈련시킨다. 이후 최적화 과정을 거쳐 예측 소음의 반대 파형을 생성 및 출력을 통해 ANC 를 구현한다.

• Journal of KIISE:Software and Applications
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• v.30 no.10
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• pp.973-982
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• 2003

This paper presents an efficient method for automatically detecting objects in a given image. The GHT is a robust template matching algorithm for automatic object detection in order to find objects of various shapes. Many different templates are applied by the GHT in order to find objects of various shapes and size. Every boundary detected by the GHT scan be used as an initial outline for more precise contour-finding techniques. The main weakness of the GHT is the excessive time and memory requirements. In order to overcome this drawback, the proposed algorithm uses a multiresolution search by scaling down the original image to half-sized and quarter-sized images. Using the information from the first iterative GHT on a quarter-sized image, the range of nuclear sizes is determined to limit the parameter space of the half-sized image. After the second iterative GHT on the half-sized image, nuclei are detected by the fine search and segmented with edge information which helps determine the exact boundary. The experimental results show that this method gives reduction in computation time and memory usage without loss of accuracy.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.91-100
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• 2016

In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.