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http://dx.doi.org/10.5573/ieie.2016.53.6.091

Image Cache for FPGA-based Real-time Image Warping  

Choi, Yong Joon (Dept. of Electrical and Information Eng., Seoul National University of Science and Technology)
Ryoo, Jung Rae (Dept. of Electrical and Information Eng., Seoul National University of Science and Technology)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.6, 2016 , pp. 91-100 More about this Journal
Abstract
In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.
Keywords
real-time image warping; image cache; bilinear interpolation; memory access rate;
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Times Cited By KSCI : 4  (Citation Analysis)
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