• Journal of information and communication convergence engineering
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• v.13 no.1
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• pp.27-35
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• 2015

Multiprecision multiplication is the most expensive operation in public key-based cryptography. Therefore, many multiplication methods have been studied intensively for several decades. In Workshop on Cryptographic Hardware and Embedded Systems 2011 (CHES2011), a novel multiplication method called 'operand caching' was proposed. This method reduces the number of required load instructions by caching the operands. However, it does not provide full operand caching when changing the row of partial products. To overcome this problem, a novel method, that is, 'consecutive operand caching' was proposed in Workshop on Information Security Applications 2012 (WISA2012). It divides a multiplication structure into partial products and reconstructs them to share common operands between previous and next partial products. However, there is still room for improvement; therefore, we propose a finely designed operand-caching mode to minimize useless memory accesses when the first row is changed. Finally, we reduce the number of memory access instructions and boost the speed of the overall multiprecision multiplication for public key cryptography.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• ETRI Journal
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• v.32 no.4
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• pp.638-641
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• 2010

With the growth of memory capacity and density, memory testing and repair with the goal of yield improvement have become more important. Therefore, the development of high efficiency redundancy analysis algorithms is essential to improve yield rate. In this letter, we propose an improved built-in redundancy analysis (BIRA) algorithm with a minimized binary search tree made by simple calculations. The tree is constructed until finding a solution from the most probable branch. This greatly reduces the search spaces for a solution. The proposed BIRA algorithm results in 100% repair efficiency and fast redundancy analysis.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.5
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• pp.658-663
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• 1999

2D sliced CT images hardly express the human disease in a space. This space expression can be reconstructed into 3D image by piling up the CT sliced image in succession. In medical image, in order to get the reconstructed 3D images, expensive system or much calculation time is needed. But by changing the method of reconstruction procedure and limit the range, the reconstruction time could be reduced. In this study, to reduce the processing time and memory, we suggested a method of interpolation and ray casting processing at the same time in a limited range. Such a limited range processing have advantages that we could reduce the unnecessary interpolation and ray casting. Through a experiment, it is founded that the reconstruction time and the memory was much reduced.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3055-3063
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• 2000

In this paper, a task duplication based heuristic scheduling algorithm is proposed to solve the problem of task scheduling on Shared Memory Multiporcessors (SMM). The proposed algorithm pre-allocates network resources so as to avoid potential communication conlhct, and the algorithm uses heuristies to select duplication tasks so as to recuce of a multiprocessors, and generates scheduling accorting to the available number of processors ina system. The proposed algorithm has been applied to some practical task graphs in the simulation, and the results show that the proposed algorithm achieves considerable performance improvement, in respect of schedule length.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.492-494
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• 1993

CMAC (Cerebeller Model Articulation Controller) is kind of Neural Networks that imitate the human cerebellum. For storage and retrieval of learned data, the input of CMAC is used as a key to determine the memory location. he learned information is distributively stored in physical memory. The learning of CMAC is very fast and converged well, therefore, it effects the application of Pattern Recognition. Through the our experiment of Pattern Recognition, we will prove that CMAC is very suitable for On-line real time processing and incremental learning of Neural Networks.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.5035-5048
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• 2016

Nano scale networks are futuristic networks deemed as enablers for the Internet of Nano Things, Body area nano networks, target tracking, anomaly/ abnormality detection at molecular level and neuronal therapy / drug delivery applications. Molecular communication is considered the most compatible communication technology for nano devices. However, connectivity in such networks is very low due to inter-symbol interference (ISI). Few research papers have addressed the issue of ISI mitigation in molecular communication. However, many of these methods are not adaptive to dynamic environmental conditions. This paper presents an enhancement over original Memory-1 ISI cancellation scheme using maximum likelihood estimation of a channel parameter (λ) to make it adaptable to variable channel conditions. Results of the Monte Carlo simulation show that, the connectivity (P_conn) improves by 28% for given simulation parameters and environmental conditions by using enhanced Memory-1 cancellation method. Moreover, this ISI mitigation method allows reduction in symbol time (Ts) up to 50 seconds i.e. an improvement of 75% is achieved.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.301-308
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• 2003

In this paper, we propose a multicast ATM switch that reduces traffic load by using the method of storing unicast cells and multicast cells separately according to the type of the cells. The switch is based on a shared memory type to reduce HOL blocking and deadlock. In the proposed switch, we use a control scheme that schedules stored cells to output ports to reduce the loss of traffic cells and to output effectively. We analyzed the Performance of the proposed switch through the computer simulation and the results have shown the effectiveness of the switch.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.21-22
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• 2013

가상화 기술은 하드웨어 위에서 여러 운영체제를 동작시키면서, 시스템의 활용률을 극대화 시키는 기술이므로 여러 분야에서 각광받고 있다. 가상화는 시스템 위험성 전파 등을 줄임으로써, 보안 노출을 막는 등 여러 장점들이 있다. 하지만, 게스트머신에서 하이퍼바이저로의 잦은 스위치는 가상화 성능을 떨어트린다. 또한, 다수의 가상머신에서 공유될 수 있는 페이지들에 대한 메모리 중복 문제도 존재한다. 우리는 가상화 환경에서 VMEXIT를 줄이고, 메모리를 절약할 수 있는 메모리 중복제거 기술을 제안하고, 이를 정성적으로 성능 평가를 진행하였다.

• Therapeutic Science for Rehabilitation
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• v.10 no.4
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• pp.39-52
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• 2021

Objective : This study aimed to identify the characteristics and analyze the quality of studies on memory improvement using a single-subject research design. Methods : Six studies were selected through the Research Information Sharing Service (RISS), Korean Studies Information Service System (KISS), and National Digital Science Library (NDSL). Keywords were memory training, stroke, early dementia, mild cognitive impairment, and single-subject research design. The characteristics and quality levels were analyzed between January 2011 and October 2020. Results : Regarding the quality level, the middle level (7-10 points) was 66.7% of the four articles, and the high level (11-14 points) was 33.3% of the two articles. Reversal designs were used in all studies. Independent variables were errorless learning, smartphone application, cognitive training system (CoTras), spaced retrieval training (SRT) with errorless learning, spaced retrieval training, and iPad applications. The dependent variables included memory, attention, electroencephalogram, instrumental activities of daily living, depression etc., which increased after the intervention. The total session, study period, and intervention time were varied. Conclusion : In single-subject research design related to memory training, occupational therapy intervention was confirmed as an effective method for improving memory and attention. The quality level of single-subject research design was moderate or higher, and high-quality level of studies should be conducted by additional design to increase the validity in the future.