• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.119-124
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• 1998

Block Matching Motion Estimation(BMME) Algorithm is demands a very large amount of computing power and have been proposed many fast algorithms. These algorithms are many problem that larger size of VLSI scale due to non-localized search block data and problem of non-reuse of input data for each processing step. In this paper, we designed systolic arry of high processing capacity, constraints input output pin size and reuse of input data for small VLSI size. The proposed systolic array is optimized memory access time because of iterative reuse of input data on search block and become independent of problem size due to increase of algorithm's parallelism and total processing elements connection is localized spatial and temporal. The designed systolic array is reduced O(N6) time complexity to O(N3) on moving vector and has O(N) input/output pin size.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.2276-2291
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• 2017

Data protection of removable storage devices is an important issue in information security. Unfortunately, most existing data protection mechanisms are aimed at protecting computer platform which is not suitable for ultra-low-power devices. To protect the flash disk appropriately and efficiently, we propose a trust based USB flash disk, named UTrustDisk. The data protection technologies in UTrustDisk include data authentication protocol, data confidentiality protection and data leakage prevention. Usually, the data integrity protection scheme is the bottleneck in the whole system and we accelerate it by WH universal hash function and speculative caching. The speculative caching will cache the potential hot chunks for reducing the memory bandwidth pollution. We adopt the symmetric encryption algorithm to protect data confidentiality. Before mounting the UTrustDisk, we will run a trusted virtual domain based lightweight virtual machine for preventing information leakage. Besides, we prove formally that UTrustDisk can prevent sensitive data from leaking out. Experimental results show that our scheme's average writing throughput is 44.8% higher than that of NH scheme, and 316% higher than that of SHA-1 scheme. And the success rate of speculative caching mechanism is up to 94.5% since the access pattern is usually sequential.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3B
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• pp.339-348
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• 2004

Packet classification is an important factor to support various services such as QoS guarantee and VPN for users in Internet. Packet classification is a searching process for best matching rule on rule tables by employing multi-field such as source address, protocol, and port number as well as destination address in If header. In this paper, we propose hardware based packet classification algorithm by employing tree bitmap of multi-bit trio. We divided prefixes of searching fields and rule into multi-bit stride, and perform a rule searching with multi-bit of fixed size. The proposed scheme can reduce the access times taking for rule search by employing indexing key in a fixed size of upper bits of rule prefixes. We also employ a marker prefixes in order to remove backtracking during searching a rule. In this paper, we generate two dimensional random rule set of source address and destination address using routing tables provided by IPMA Project, and compare its memory usages and performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1582-1589
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• 2006

A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. %is paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The nv mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.

• 한국HCI학회:학술대회논문집
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• 2008.02b
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• pp.460-464
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• 2008

To improve and optimize user interfaces of the system, the accurate understanding of users' behavior is an essential prerequisite. Direct questions depend on user' s ambiguous memory and usability tests depend on the researchers' intention instead of users'. Furthermore, they do not provide with natural context of use. In this paper we described the work which examined users' behavior through log analysis in their own environment. 50 users were recruited by consumer segmentation and they were downloaded logging-software in their mobile phone. After two weeks, logged data were gathered and analyzed. The complementary methods such as a user diary and an interview were conducted. The result of the analysis showed the frequency of menu and key access, used time, data storage and several usage patterns. Also, it was found that users could be segmented into new groups by their usage patterns. The improvement of the mobile phone user interface was proposed based on the result of this study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.425-432
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• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.624-627
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• 2003

The BLT thin-films were one of the promising ferroelectric materials with a good leakage current and degradation behavior on Pt electrode. The BLT target was sintered at $1100^{\circ}C$ for 4 hours at the air ambient. $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin-film deposited on $Pt/Ti/SIO_2/Si$ wafer by rf magnetron sputtering method. At annealed $700^{\circ}C$, (117) and (006) peaks appeared the high intensity. The hysteresis loop of the BLT thin films showed that the remanent polarization ($2Pr=Pr^+-Pr^-$) was $16uC/cm^2$ and leakage current density was $1.8{\times}10^{-9}A/cm^2$ at 50 kV/cm with coersive electric field when BLT thin-films were annealed at $700^{\circ}C$. Also, the thin film showed fatigue property at least up to $10^{10}$ switching bipolar pulse cycles under 7 V. Therefore, we induce access to optimum fabrication condition of memory device application by rf-magnetron sputtering method in this report.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.257-257
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• 2010

최근 저항 변화 메모리는 종래의 비휘발성 기억소자인 Flash memory보다 access time(writing)이 105배 이상 빠르고, DRAM과 같이 2~5 V 이하의 낮은 전압 특성 및 간단한 제조 공정 등으로 차세대 비휘발성 메모리 소자로 주목 받고 있지만, 여전히 소자의 Endurance 및 Retention 특성 등의 신뢰성 문제를 해결해야 할 과제로 안고 있다. 이러한 문제점들을 해결하기 위해 페로브스카이트계 산화물 또는 이원 산화물 등의 다양한 저항 변화 물질에 대한 연구가 진행되고 있다. 하지만, 현재 주로 연구되고 있는 금속 산화물계 물질들은 그 제조 공정상 산소에 의한 다수의 산소 디펙트 형성과 제작 시 쉽게 발생할 수 있는 표면 오염의 문제점을 안고 있다. 본 연구는 기존의 금속 산화물계 박막의 제조 공정에서 발생하는 문제점을 해결하기 위해 질화물계 박막을 저항변화 물질로 도입함으로써, 기존의 저항 변화 물질의 장점인 간단한 공정 및 저전압/고속 동작 특성을 동일하게 유지 할 뿐 아니라, 그 제조 공정상 발생하는 다수의 산소 디펙트와 표면 오염의 문제를 해결함으로써, 보다 고효율을 가지며 재현성이 우수한 메모리 소자를 구현 하고자 한다 [1, 2]. 본 연구를 위해 Pt/AlN/Pt 구조의 Metal/Insulator/Metal(MIM) 저항 변화 메모리를 제작 하였다. 최적의 저항 변화 특성 조건을 확인하기 위해 70~200nm까지 두께 구분과 N2 가스 분위기의 열처리 온도를 $200{\sim}600^{\circ}C$까지 진행 하였다. 본 소자의 저항 변화 특성 실험은 Keithley 4200-SCS을 이용하여 진행 하였다. 실험 결과, AlN의 최적의 두께 및 열처리 온도 조건은 130nm/$500^{\circ}C$였으며, 안정적인 unipolar 저항 변화 특성을 확인 활 수 있었다.