• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권8호
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• International Journal of Contents
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• 제5권2호
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• 대한임베디드공학회논문지
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• 제11권6호
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• 한국광학회지
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• 제14권1호
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• pp.65-71
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• 2003

국소 홀로그램 기록방법에서 저장밀도를 높이기 위해서는 각 홀로그램은 이웃한 홀로그램들과 가급적 가깝게 기록되어야 한다. 이 경우에 두 인접한 홀로그램의 기준빔들은 공간적으로 겹칠 수 있다. 본 논문에서는 공간다중화를 위한 기준빔의 이동거리에 대해서 겹침을 최소화하는 최적의 기준빔 폭이 존재함을 시물레이션 및 실험적으로 보인다 따라서, 저장밀도를 높임에 따르는 국소 홀로그램의 장점의 희생을 최소화할 수 있다.

• 전자공학회논문지A
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• 제33A권4호
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• 센서학회지
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• 제12권1호
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• pp.51-56
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• 2003

We describe a charge pump circuit using VCO (voltage controlled oscillator) for storing information into local memories in neural networks. The VCO is used for adjusting the output voltage of the charge pump to the reference voltage and for reducing the fluctuation generated by the clocking scheme. The charge pump circuit is simulated by using Hynix 0.35um CMOS process parameters. The proposed charge pump operates properly regardless to the temperature and the supply voltage variation.

• Journal of Magnetics
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• 제8권1호
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• pp.60-69
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• 2003

A review of mechanical sensing techniques based on magnetic methods is presented, with special reference to magnetoelastic strain gauges and force sensors. A novel strain sensor based on soft amorphous ribbons is described. Other types of magnetic sensors, for the measurement of torque and displacement are briefly discussed. An overview of magnetic actuators based on giant magnetostrictive materials, with some practical examples, is presented. Recent advances in the development and application of magnetic shape memory materials are discussed, together with the analysis of recent studies for the description of magnetic shape memory phenomena.

• 제어로봇시스템학회논문지
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• 제13권4호
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• pp.279-285
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• 2007

The objective of the research is two fold. The first is to design and propose a stable and robust learning control algorithm. The controller is CMAC Learning Controller which consists of a model-based controller, such as LQR or PID, as a reference control and a CMAC. The second objective is to implement a reference control and CMAC at two different sampling rates. Generally, a conventional controller is designed based on a mathematical plant model. However, increasing complexity of the plant and accuracy requirement on mathematical models nearly prohibits the application of the conventional controller design approach. To avoid inherent complexity and unavoidable uncertainty in modeling, biology mimetic methods have been developed. One of such attempts is Cerebellar Model Articulation Computer(CMAC) developed by Albus. CMAC has two main disadvantages. The first disadvantage of CMAC is increasing memory requirement with increasing number of input variables and with increasing accuracy demand. The memory needs can be solved with cheap memories due to recent development of new memory technology. The second disadvantage is a demand for processing powers which could be an obstacle especially when CMAC should be implemented in real-time. To overcome the disadvantages of CMAC, we propose CMAC learning controller with multiple sampling rates. With this approach a conventional controller which is a reference to CMAC at high enough sampling rate but CMAC runs at the processor's unoccupied time. To show efficiency of the proposed method, an inverted pendulum controller is designed and implemented. We also demonstrate it's possibility as an industrial control solution and robustness against a modeling uncertainty.